Commit 4fb1cf3a authored by Chunming Zhou's avatar Chunming Zhou Committed by Alex Deucher
Browse files

drm/amdgpu: set page table depth by num_level 



Signed-off-by: default avatarChunming Zhou <David1.Zhou@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 36f8c1f9

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+2 −1
Original line number Diff line number Diff line
@@ -195,7 +195,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) 
	for (i = 0; i <= 14; i++) {

		tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

				    adev->vm_manager.num_level);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+1 −1
Original line number Diff line number Diff line
@@ -216,7 +216,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) 
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

				ENABLE_CONTEXT, 1);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

				PAGE_TABLE_DEPTH, 1);

				PAGE_TABLE_DEPTH, adev->vm_manager.num_level);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

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