drm/i915/gen9: Disable WM if corresponding latency is 0 (4f947386) · Commits · 戴 / test

According to updated BSpec, If level 1 or any higher level has a value of 0x00, that level and any higher levels are unused and the associated watermark registers must not be enabled. This patch checks for latency 0 for level >=1 and does not enable WM corresponding to level m | m>=n, if level n (n != 0) has a 0us latency. v2: Satheesh's review comments - zero-out latency values (for all higher levels if latency of given level is zero ) in read_wm_latency() function itself v3: removed redundant check as per Satheesh's observation. v4: rebase on top before merging (Damien) v5: Rebase on top of the default value removal (Ville) Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v3) Reviewed-by:

Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:

Damien Lespiau <damien.lespiau@intel.com> Signed-off-by:

Vandana Kannan <vandana.kannan@intel.com> Signed-off-by:

Daniel Vetter <daniel.vetter@ffwll.ch>

drivers/gpu/drm/i915/intel_pm.c

+12 −2

Original line number	Diff line number	Diff line
		@@ -2285,7 +2285,7 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])

		if (IS_GEN9(dev)) {
		uint32_t val;
		int ret;
		int ret, i;
		int level, max_level = ilk_wm_max_level(dev);

		/* read the first set of memory latencies[0:3] */
		@@ -2338,12 +2338,22 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
		* we always add 2us there.
		* - For levels >=1, punit returns 0us latency when they are
		* disabled, so we respect that and don't add 2us then
		*
		* Additionally, if a level n (n > 1) has a 0us latency, all
		* levels m (m >= n) need to be disabled. We make sure to
		* sanitize the values out of the punit to satisfy this
		* requirement.
		*/
		wm[0] += 2;
		for (level = 1; level <= max_level; level++)
		if (wm[level] != 0)
		wm[level] += 2;
		else {
		for (i = level + 1; i <= max_level; i++)
		wm[i] = 0;

		break;
		}
		} else if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev)) {
		uint64_t sskpd = I915_READ64(MCH_SSKPD);

		@@ -3285,7 +3295,7 @@ static bool skl_compute_plane_wm(struct skl_pipe_wm_parameters *p,
		uint32_t method1, method2, plane_bytes_per_line;
		uint32_t result_bytes;

		if (!p->active \|\| !p_params->enabled)
		if (mem_value == 0 \|\| !p->active \|\| !p_params->enabled)
		return false;

		method1 = skl_wm_method1(p->pixel_rate,

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