clk: qcom: Add qspi (Quad SPI) clocks for sdm845 (4f83d9b8) · Commits · 戴 / test

drivers/clk/qcom/gcc-sdm845.c

+56 −0

Original line number	Diff line number	Diff line
		@@ -356,6 +356,28 @@ static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
		},
		};

		static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
		F(19200000, P_BI_TCXO, 1, 0, 0),
		F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
		F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
		F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
		{ }
		};

		static struct clk_rcg2 gcc_qspi_core_clk_src = {
		.cmd_rcgr = 0x4b008,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qspi_core_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_qspi_core_clk_src",
		.parent_names = gcc_parent_names_0,
		.num_parents = 4,
		.ops = &clk_rcg2_floor_ops,
		},
		};

		static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
		F(9600000, P_BI_TCXO, 2, 0, 0),
		F(19200000, P_BI_TCXO, 1, 0, 0),
		@@ -1933,6 +1955,37 @@ static struct clk_branch gcc_qmip_video_ahb_clk = {
		},
		};

		static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
		.halt_reg = 0x4b000,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x4b000,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_qspi_cnoc_periph_ahb_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_qspi_core_clk = {
		.halt_reg = 0x4b004,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x4b004,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_qspi_core_clk",
		.parent_names = (const char *[]){
		"gcc_qspi_core_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
		.halt_reg = 0x17030,
		.halt_check = BRANCH_HALT_VOTED,
		@@ -3381,6 +3434,9 @@ static struct clk_regmap *gcc_sdm845_clocks[] = {
		[GPLL4] = &gpll4.clkr,
		[GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
		[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
		[GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
		[GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
		[GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
		};

		static const struct qcom_reset_map gcc_sdm845_resets[] = {

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