Commit 4f8036a2 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Make HAS_DDI and HAS_PCH_LPT_LP only take dev_priv 



This saves 3248 bytes of .rodata strings.

v2: Add parantheses around dev_priv. (Ville Syrjala)

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarDavid Weinehall <david.weinehall@linux.intel.com>
Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: default avatarJani Nikula <jani.nikula@linux.intel.com>
Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Acked-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
parent 3b3f1650

drivers/gpu/drm/i915/i915_drv.h

+5 −3
Original line number Diff line number Diff line
@@ -2811,7 +2811,7 @@ struct drm_i915_cmd_table { 


#define HAS_DP_MST(dev)	(INTEL_INFO(dev)->has_dp_mst)



#define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)

#define HAS_DDI(dev_priv)	((dev_priv)->info.has_ddi)

#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)

#define HAS_PSR(dev)		(INTEL_INFO(dev)->has_psr)

#define HAS_RUNTIME_PM(dev)	(INTEL_INFO(dev)->has_runtime_pm)
@@ -2850,8 +2850,10 @@ struct drm_i915_cmd_table { 
#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)

#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)

#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)

#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)

#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)

#define HAS_PCH_LPT_LP(dev_priv) \

	((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)

#define HAS_PCH_LPT_H(dev_priv) \

	((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)

#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)

#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)

#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)

drivers/gpu/drm/i915/intel_crt.c

+5 −5
Original line number Diff line number Diff line
@@ -280,13 +280,13 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder, 
				     struct intel_crtc_state *pipe_config,

				     struct drm_connector_state *conn_state)

{

	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);



	if (HAS_PCH_SPLIT(dev))

	if (HAS_PCH_SPLIT(dev_priv))

		pipe_config->has_pch_encoder = true;



	/* LPT FDI RX only supports 8bpc. */

	if (HAS_PCH_LPT(dev)) {

	if (HAS_PCH_LPT(dev_priv)) {

		if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {

			DRM_DEBUG_KMS("LPT only supports 24bpp\n");

			return false;
@@ -296,7 +296,7 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder, 
	}



	/* FDI must always be 2.7 GHz */

	if (HAS_DDI(dev))

	if (HAS_DDI(dev_priv))

		pipe_config->port_clock = 135000 * 2;



	return true;
@@ -917,7 +917,7 @@ void intel_crt_init(struct drm_device *dev) 
	if (I915_HAS_HOTPLUG(dev) &&

	    !dmi_check_system(intel_spurious_crt_detect))

		crt->base.hpd_pin = HPD_CRT;

	if (HAS_DDI(dev)) {

	if (HAS_DDI(dev_priv)) {

		crt->base.port = PORT_E;

		crt->base.get_config = hsw_crt_get_config;

		crt->base.get_hw_state = intel_ddi_get_hw_state;

drivers/gpu/drm/i915/intel_display.c

+25 −24
Original line number Diff line number Diff line
@@ -1187,19 +1187,17 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, 
			onoff(state), onoff(cur_state));

}



void assert_panel_unlocked(struct drm_i915_private *dev_priv,

			   enum pipe pipe)

void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)

{

	struct drm_device *dev = &dev_priv->drm;

	i915_reg_t pp_reg;

	u32 val;

	enum pipe panel_pipe = PIPE_A;

	bool locked = true;



	if (WARN_ON(HAS_DDI(dev)))

	if (WARN_ON(HAS_DDI(dev_priv)))

		return;



	if (HAS_PCH_SPLIT(dev)) {

	if (HAS_PCH_SPLIT(dev_priv)) {

		u32 port_sel;



		pp_reg = PP_CONTROL(0);
@@ -1209,7 +1207,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, 
		    I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)

			panel_pipe = PIPE_B;

		/* XXX: else fix for eDP */

	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {

	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		/* presumably write lock depends on pipe, not port select */

		pp_reg = PP_CONTROL(pipe);

		panel_pipe = pipe;
@@ -5696,13 +5694,13 @@ static enum intel_display_power_domain port_to_aux_power_domain(enum port port) 
enum intel_display_power_domain

intel_display_port_power_domain(struct intel_encoder *intel_encoder)

{

	struct drm_device *dev = intel_encoder->base.dev;

	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);

	struct intel_digital_port *intel_dig_port;



	switch (intel_encoder->type) {

	case INTEL_OUTPUT_UNKNOWN:

		/* Only DDI platforms should ever use this output type */

		WARN_ON_ONCE(!HAS_DDI(dev));

		WARN_ON_ONCE(!HAS_DDI(dev_priv));

	case INTEL_OUTPUT_DP:

	case INTEL_OUTPUT_HDMI:

	case INTEL_OUTPUT_EDP:
@@ -5723,7 +5721,7 @@ intel_display_port_power_domain(struct intel_encoder *intel_encoder) 
enum intel_display_power_domain

intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)

{

	struct drm_device *dev = intel_encoder->base.dev;

	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);

	struct intel_digital_port *intel_dig_port;



	switch (intel_encoder->type) {
@@ -5736,7 +5734,7 @@ intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) 
		 * what's the status of the given connectors, play safe and

		 * run the DP detection too.

		 */

		WARN_ON_ONCE(!HAS_DDI(dev));

		WARN_ON_ONCE(!HAS_DDI(dev_priv));

	case INTEL_OUTPUT_DP:

	case INTEL_OUTPUT_EDP:

		intel_dig_port = enc_to_dig_port(&intel_encoder->base);
@@ -9196,7 +9194,8 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, 


	if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))

		with_spread = true;

	if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))

	if (WARN(HAS_PCH_LPT_LP(dev_priv) &&

	    with_fdi, "LP PCH doesn't have FDI\n"))

		with_fdi = false;



	mutex_lock(&dev_priv->sb_lock);
@@ -9219,7 +9218,7 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, 
		}

	}



	reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;

	reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;

	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);

	tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;

	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
@@ -9235,7 +9234,7 @@ static void lpt_disable_clkout_dp(struct drm_device *dev) 


	mutex_lock(&dev_priv->sb_lock);



	reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;

	reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;

	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);

	tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;

	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
@@ -10203,7 +10202,7 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv) 


	DRM_DEBUG_KMS("Enabling package C8+\n");



	if (HAS_PCH_LPT_LP(dev)) {

	if (HAS_PCH_LPT_LP(dev_priv)) {

		val = I915_READ(SOUTH_DSPCLK_GATE_D);

		val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;

		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
@@ -10223,7 +10222,7 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv) 
	hsw_restore_lcpll(dev_priv);

	lpt_init_pch_refclk(dev);



	if (HAS_PCH_LPT_LP(dev)) {

	if (HAS_PCH_LPT_LP(dev_priv)) {

		val = I915_READ(SOUTH_DSPCLK_GATE_D);

		val |= PCH_LP_PARTITION_LEVEL_DISABLE;

		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
@@ -10845,7 +10844,7 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, 
		}

		cntl |= pipe << 28; /* Connect to correct pipe */



		if (HAS_DDI(dev))

		if (HAS_DDI(dev_priv))

			cntl |= CURSOR_PIPE_CSC_ENABLE;



		if (plane_state->base.rotation == DRM_ROTATE_180)
@@ -12745,6 +12744,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, 
				   const char *context)

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct drm_plane *plane;

	struct intel_plane *intel_plane;

	struct intel_plane_state *state;
@@ -12827,7 +12827,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, 
			      pipe_config->dpll_hw_state.ctrl1,

			      pipe_config->dpll_hw_state.cfgcr1,

			      pipe_config->dpll_hw_state.cfgcr2);

	} else if (HAS_DDI(dev)) {

	} else if (HAS_DDI(dev_priv)) {

		DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",

			      pipe_config->dpll_hw_state.wrpll,

			      pipe_config->dpll_hw_state.spll);
@@ -12905,7 +12905,7 @@ static bool check_digital_port_conflicts(struct drm_atomic_state *state) 
		switch (encoder->type) {

			unsigned int port_mask;

		case INTEL_OUTPUT_UNKNOWN:

			if (WARN_ON(!HAS_DDI(dev)))

			if (WARN_ON(!HAS_DDI(to_i915(dev))))

				break;

		case INTEL_OUTPUT_DP:

		case INTEL_OUTPUT_HDMI:
@@ -13729,7 +13729,7 @@ intel_modeset_verify_disabled(struct drm_device *dev) 


static void update_scanline_offset(struct intel_crtc *crtc)

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);



	/*

	 * The scanline counter increments at the leading edge of hsync.
@@ -13749,7 +13749,7 @@ static void update_scanline_offset(struct intel_crtc *crtc) 
	 * there's an extra 1 line difference. So we need to add two instead of

	 * one to the value.

	 */

	if (IS_GEN2(dev)) {

	if (IS_GEN2(dev_priv)) {

		const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;

		int vtotal;
@@ -13758,7 +13758,7 @@ static void update_scanline_offset(struct intel_crtc *crtc) 
			vtotal /= 2;



		crtc->scanline_offset = vtotal - 1;

	} else if (HAS_DDI(dev) &&

	} else if (HAS_DDI(dev_priv) &&

		   intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {

		crtc->scanline_offset = 2;

	} else
@@ -15327,11 +15327,12 @@ static bool intel_crt_present(struct drm_device *dev) 
	if (IS_CHERRYVIEW(dev))

		return false;



	if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)

	if (HAS_PCH_LPT_H(dev_priv) &&

	    I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)

		return false;



	/* DDI E can't be used if DDI A requires 4 lanes */

	if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)

	if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)

		return false;



	if (!dev_priv->vbt.int_crt_support)
@@ -15405,7 +15406,7 @@ static void intel_setup_outputs(struct drm_device *dev) 
		intel_ddi_init(dev, PORT_C);



		intel_dsi_init(dev);

	} else if (HAS_DDI(dev)) {

	} else if (HAS_DDI(dev_priv)) {

		int found;



		/*

drivers/gpu/drm/i915/intel_dp.c

+8 −8
Original line number Diff line number Diff line
@@ -1565,7 +1565,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, 


	max_clock = common_len - 1;



	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)

	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)

		pipe_config->has_pch_encoder = true;



	pipe_config->has_drrs = false;
@@ -1707,7 +1707,7 @@ found: 
		to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;

	}



	if (!HAS_DDI(dev))

	if (!HAS_DDI(dev_priv))

		intel_dp_set_clock(encoder, pipe_config);



	return true;
@@ -2632,7 +2632,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, 
		DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",

			      dp_train_pat & DP_TRAINING_PATTERN_MASK);



	if (HAS_DDI(dev)) {

	if (HAS_DDI(dev_priv)) {

		uint32_t temp = I915_READ(DP_TP_CTL(port));



		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
@@ -3339,7 +3339,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp) 
	uint32_t signal_levels, mask = 0;

	uint8_t train_set = intel_dp->train_set[0];



	if (HAS_DDI(dev)) {

	if (HAS_DDI(dev_priv)) {

		signal_levels = ddi_signal_levels(intel_dp);



		if (IS_BROXTON(dev))
@@ -3398,7 +3398,7 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) 
	enum port port = intel_dig_port->port;

	uint32_t val;



	if (!HAS_DDI(dev))

	if (!HAS_DDI(dev_priv))

		return;



	val = I915_READ(DP_TP_CTL(port));
@@ -3433,7 +3433,7 @@ intel_dp_link_down(struct intel_dp *intel_dp) 
	struct drm_i915_private *dev_priv = to_i915(dev);

	uint32_t DP = intel_dp->DP;



	if (WARN_ON(HAS_DDI(dev)))

	if (WARN_ON(HAS_DDI(dev_priv)))

		return;



	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
@@ -5659,7 +5659,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 
	else

		intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;



	if (HAS_DDI(dev))

	if (HAS_DDI(dev_priv))

		intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;



	/* Preserve the current hw state. */
@@ -5701,7 +5701,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 


	intel_connector_attach_encoder(intel_connector, intel_encoder);



	if (HAS_DDI(dev))

	if (HAS_DDI(dev_priv))

		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;

	else

		intel_connector->get_hw_state = intel_connector_get_hw_state;

drivers/gpu/drm/i915/intel_dpll_mgr.c

+2 −2
Original line number Diff line number Diff line
@@ -1855,7 +1855,7 @@ void intel_shared_dpll_init(struct drm_device *dev) 
		dpll_mgr = &skl_pll_mgr;

	else if (IS_BROXTON(dev))

		dpll_mgr = &bxt_pll_mgr;

	else if (HAS_DDI(dev))

	else if (HAS_DDI(dev_priv))

		dpll_mgr = &hsw_pll_mgr;

	else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))

		dpll_mgr = &pch_pll_mgr;
@@ -1883,7 +1883,7 @@ void intel_shared_dpll_init(struct drm_device *dev) 
	BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);



	/* FIXME: Move this to a more suitable place */

	if (HAS_DDI(dev))

	if (HAS_DDI(dev_priv))

		intel_ddi_pll_init(dev);

}

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