Commit 4f6dd8d6 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'for-upstream/mali-dp' of git://linux-arm.org/linux-ld into drm-next 

I have accumulated some patches as we went through some internal testing
for mali-dp and I was waiting for the YUV2RGB patches to land in your
tree.

* 'for-upstream/mali-dp' of git://linux-arm.org/linux-ld:
  drm: mali-dp: Add YUV->RGB conversion support for video layers
  drm: mali-dp: Turn off CRTC vblank when removing module.
  drm: arm: malidp: Use drm_atomic_helper_shutdown() to disable planes on removal
  drm: arm: malidp: Don't destroy planes manually in error handlers
  drm/mali-dp: Fix malidp_atomic_commit_hw_done() for event sending.
  drm/arm/malidp: Disable pixel alpha blending for colors that do not have alpha
  drm: mali-dp: Fix bug on scaling with rotation
  drm/mali-dp: Don't enable scaling engine for planes that only rotate.
  drm: mali-dp: Uninitialized variable in malidp_se_check_scaling()
  drm/mali-dp: Align pitch size to be multiple of bus burst read size.
  drm/mali-dp: Rotated planes need a larger pitch size.
parents 287d2ac3 6e810eb5

drivers/gpu/drm/arm/malidp_crtc.c

+10 −10
Original line number Original line Diff line number Diff line
@@ -288,8 +288,14 @@ static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc, 
		s->enhancer_enable = ((h_upscale_factor >> 16) >= 2 ||

		s->enhancer_enable = ((h_upscale_factor >> 16) >= 2 ||

				      (v_upscale_factor >> 16) >= 2);

				      (v_upscale_factor >> 16) >= 2);





		if (pstate->rotation & MALIDP_ROTATED_MASK) {

			s->input_w = pstate->src_h >> 16;

			s->input_h = pstate->src_w >> 16;

		} else {

			s->input_w = pstate->src_w >> 16;

			s->input_w = pstate->src_w >> 16;

			s->input_h = pstate->src_h >> 16;

			s->input_h = pstate->src_h >> 16;

		}



		s->output_w = pstate->crtc_w;

		s->output_w = pstate->crtc_w;

		s->output_h = pstate->crtc_h;

		s->output_h = pstate->crtc_h;
@@ -525,14 +531,13 @@ int malidp_crtc_init(struct drm_device *drm) 




	if (!primary) {

	if (!primary) {

		DRM_ERROR("no primary plane found\n");

		DRM_ERROR("no primary plane found\n");

		ret = -EINVAL;

		return -EINVAL;

		goto crtc_cleanup_planes;

	}

	}





	ret = drm_crtc_init_with_planes(drm, &malidp->crtc, primary, NULL,

	ret = drm_crtc_init_with_planes(drm, &malidp->crtc, primary, NULL,

					&malidp_crtc_funcs, NULL);

					&malidp_crtc_funcs, NULL);

	if (ret)

	if (ret)

		goto crtc_cleanup_planes;

		return ret;





	drm_crtc_helper_add(&malidp->crtc, &malidp_crtc_helper_funcs);

	drm_crtc_helper_add(&malidp->crtc, &malidp_crtc_helper_funcs);

	drm_mode_crtc_set_gamma_size(&malidp->crtc, MALIDP_GAMMA_LUT_SIZE);

	drm_mode_crtc_set_gamma_size(&malidp->crtc, MALIDP_GAMMA_LUT_SIZE);
@@ -542,9 +547,4 @@ int malidp_crtc_init(struct drm_device *drm) 
	malidp_se_set_enh_coeffs(malidp->dev);

	malidp_se_set_enh_coeffs(malidp->dev);





	return 0;

	return 0;



crtc_cleanup_planes:

	malidp_de_planes_destroy(drm);



	return ret;

}
 
}

drivers/gpu/drm/arm/malidp_drv.c

+34 −17
Original line number Original line Diff line number Diff line
@@ -185,25 +185,29 @@ static int malidp_set_and_wait_config_valid(struct drm_device *drm) 




static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state)

static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state)

{

{

	struct drm_pending_vblank_event *event;

	struct drm_device *drm = state->dev;

	struct drm_device *drm = state->dev;

	struct malidp_drm *malidp = drm->dev_private;

	struct malidp_drm *malidp = drm->dev_private;





	if (malidp->crtc.enabled) {

	malidp->event = malidp->crtc.state->event;

		/* only set config_valid if the CRTC is enabled */

		if (malidp_set_and_wait_config_valid(drm))

			DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n");

	}



	event = malidp->crtc.state->event;

	if (event) {

	malidp->crtc.state->event = NULL;

	malidp->crtc.state->event = NULL;





	if (malidp->crtc.state->active) {

		/*

		 * if we have an event to deliver to userspace, make sure

		 * the vblank is enabled as we are sending it from the IRQ

		 * handler.

		 */

		if (malidp->event)

			drm_crtc_vblank_get(&malidp->crtc);



		/* only set config_valid if the CRTC is enabled */

		if (malidp_set_and_wait_config_valid(drm) < 0)

			DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n");

	} else if (malidp->event) {

		/* CRTC inactive means vblank IRQ is disabled, send event directly */

		spin_lock_irq(&drm->event_lock);

		spin_lock_irq(&drm->event_lock);

		if (drm_crtc_vblank_get(&malidp->crtc) == 0)

		drm_crtc_send_vblank_event(&malidp->crtc, malidp->event);

			drm_crtc_arm_vblank_event(&malidp->crtc, event);

		malidp->event = NULL;

		else

			drm_crtc_send_vblank_event(&malidp->crtc, event);

		spin_unlock_irq(&drm->event_lock);

		spin_unlock_irq(&drm->event_lock);

	}

	}

	drm_atomic_helper_commit_hw_done(state);

	drm_atomic_helper_commit_hw_done(state);
@@ -232,8 +236,6 @@ static void malidp_atomic_commit_tail(struct drm_atomic_state *state) 




	malidp_atomic_commit_hw_done(state);

	malidp_atomic_commit_hw_done(state);





	drm_atomic_helper_wait_for_vblanks(drm, state);



	pm_runtime_put(drm->dev);

	pm_runtime_put(drm->dev);





	drm_atomic_helper_cleanup_planes(drm, state);

	drm_atomic_helper_cleanup_planes(drm, state);
@@ -276,7 +278,7 @@ static int malidp_init(struct drm_device *drm) 




static void malidp_fini(struct drm_device *drm)

static void malidp_fini(struct drm_device *drm)

{

{

	malidp_de_planes_destroy(drm);

	drm_atomic_helper_shutdown(drm);

	drm_mode_config_cleanup(drm);

	drm_mode_config_cleanup(drm);

}

}
@@ -312,13 +314,26 @@ static int malidp_irq_init(struct platform_device *pdev) 




DEFINE_DRM_GEM_CMA_FOPS(fops);

DEFINE_DRM_GEM_CMA_FOPS(fops);





static int malidp_dumb_create(struct drm_file *file_priv,

			      struct drm_device *drm,

			      struct drm_mode_create_dumb *args)

{

	struct malidp_drm *malidp = drm->dev_private;

	/* allocate for the worst case scenario, i.e. rotated buffers */

	u8 alignment = malidp_hw_get_pitch_align(malidp->dev, 1);



	args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), alignment);



	return drm_gem_cma_dumb_create_internal(file_priv, drm, args);

}



static struct drm_driver malidp_driver = {

static struct drm_driver malidp_driver = {

	.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC |

	.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC |

			   DRIVER_PRIME,

			   DRIVER_PRIME,

	.lastclose = drm_fb_helper_lastclose,

	.lastclose = drm_fb_helper_lastclose,

	.gem_free_object_unlocked = drm_gem_cma_free_object,

	.gem_free_object_unlocked = drm_gem_cma_free_object,

	.gem_vm_ops = &drm_gem_cma_vm_ops,

	.gem_vm_ops = &drm_gem_cma_vm_ops,

	.dumb_create = drm_gem_cma_dumb_create,

	.dumb_create = malidp_dumb_create,

	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,

	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,

	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,

	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,

	.gem_prime_export = drm_gem_prime_export,

	.gem_prime_export = drm_gem_prime_export,
@@ -662,8 +677,10 @@ static void malidp_unbind(struct device *dev) 
	drm_fb_cma_fbdev_fini(drm);

	drm_fb_cma_fbdev_fini(drm);

	drm_kms_helper_poll_fini(drm);

	drm_kms_helper_poll_fini(drm);

	pm_runtime_get_sync(dev);

	pm_runtime_get_sync(dev);

	drm_crtc_vblank_off(&malidp->crtc);

	malidp_se_irq_fini(drm);

	malidp_se_irq_fini(drm);

	malidp_de_irq_fini(drm);

	malidp_de_irq_fini(drm);

	drm->irq_enabled = false;

	component_unbind_all(dev, drm);

	component_unbind_all(dev, drm);

	of_node_put(malidp->crtc.port);

	of_node_put(malidp->crtc.port);

	malidp->crtc.port = NULL;

	malidp->crtc.port = NULL;

drivers/gpu/drm/arm/malidp_drv.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -22,6 +22,7 @@ struct malidp_drm { 
	struct malidp_hw_device *dev;

	struct malidp_hw_device *dev;

	struct drm_crtc crtc;

	struct drm_crtc crtc;

	wait_queue_head_t wq;

	wait_queue_head_t wq;

	struct drm_pending_vblank_event *event;

	atomic_t config_valid;

	atomic_t config_valid;

	u32 core_id;

	u32 core_id;

};

};
@@ -59,7 +60,6 @@ struct malidp_crtc_state { 
#define to_malidp_crtc_state(x) container_of(x, struct malidp_crtc_state, base)

#define to_malidp_crtc_state(x) container_of(x, struct malidp_crtc_state, base)





int malidp_de_planes_init(struct drm_device *drm);

int malidp_de_planes_init(struct drm_device *drm);

void malidp_de_planes_destroy(struct drm_device *drm);

int malidp_crtc_init(struct drm_device *drm);

int malidp_crtc_init(struct drm_device *drm);





/* often used combination of rotational bits */

/* often used combination of rotational bits */

drivers/gpu/drm/arm/malidp_hw.c

+16 −10
Original line number Original line Diff line number Diff line
@@ -75,16 +75,16 @@ static const struct malidp_format_id malidp550_de_formats[] = { 
};

};





static const struct malidp_layer malidp500_layers[] = {

static const struct malidp_layer malidp500_layers[] = {

	{ DE_VIDEO1, MALIDP500_DE_LV_BASE, MALIDP500_DE_LV_PTR_BASE, MALIDP_DE_LV_STRIDE0 },

	{ DE_VIDEO1, MALIDP500_DE_LV_BASE, MALIDP500_DE_LV_PTR_BASE, MALIDP_DE_LV_STRIDE0, MALIDP500_LV_YUV2RGB },

	{ DE_GRAPHICS1, MALIDP500_DE_LG1_BASE, MALIDP500_DE_LG1_PTR_BASE, MALIDP_DE_LG_STRIDE },

	{ DE_GRAPHICS1, MALIDP500_DE_LG1_BASE, MALIDP500_DE_LG1_PTR_BASE, MALIDP_DE_LG_STRIDE, 0 },

	{ DE_GRAPHICS2, MALIDP500_DE_LG2_BASE, MALIDP500_DE_LG2_PTR_BASE, MALIDP_DE_LG_STRIDE },

	{ DE_GRAPHICS2, MALIDP500_DE_LG2_BASE, MALIDP500_DE_LG2_PTR_BASE, MALIDP_DE_LG_STRIDE, 0 },

};

};





static const struct malidp_layer malidp550_layers[] = {

static const struct malidp_layer malidp550_layers[] = {

	{ DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE, MALIDP_DE_LV_STRIDE0 },

	{ DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE, MALIDP_DE_LV_STRIDE0, MALIDP550_LV_YUV2RGB },

	{ DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE, MALIDP_DE_LG_STRIDE },

	{ DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE, MALIDP_DE_LG_STRIDE, 0 },

	{ DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE, MALIDP_DE_LV_STRIDE0 },

	{ DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE, MALIDP_DE_LV_STRIDE0, MALIDP550_LV_YUV2RGB },

	{ DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE, MALIDP550_DE_LS_R1_STRIDE },

	{ DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE, MALIDP550_DE_LS_R1_STRIDE, 0 },

};

};





#define SE_N_SCALING_COEFFS	96

#define SE_N_SCALING_COEFFS	96
@@ -782,9 +782,15 @@ static irqreturn_t malidp_de_irq(int irq, void *arg) 
	/* first handle the config valid IRQ */

	/* first handle the config valid IRQ */

	dc_status = malidp_hw_read(hwdev, hw->map.dc_base + MALIDP_REG_STATUS);

	dc_status = malidp_hw_read(hwdev, hw->map.dc_base + MALIDP_REG_STATUS);

	if (dc_status & hw->map.dc_irq_map.vsync_irq) {

	if (dc_status & hw->map.dc_irq_map.vsync_irq) {

		/* we have a page flip event */

		atomic_set(&malidp->config_valid, 1);

		malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, dc_status);

		malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, dc_status);

		/* do we have a page flip event? */

		if (malidp->event != NULL) {

			spin_lock(&drm->event_lock);

			drm_crtc_send_vblank_event(&malidp->crtc, malidp->event);

			malidp->event = NULL;

			spin_unlock(&drm->event_lock);

		}

		atomic_set(&malidp->config_valid, 1);

		ret = IRQ_WAKE_THREAD;

		ret = IRQ_WAKE_THREAD;

	}

	}
@@ -794,7 +800,7 @@ static irqreturn_t malidp_de_irq(int irq, void *arg) 




	mask = malidp_hw_read(hwdev, MALIDP_REG_MASKIRQ);

	mask = malidp_hw_read(hwdev, MALIDP_REG_MASKIRQ);

	status &= mask;

	status &= mask;

	if (status & de->vsync_irq)

	if ((status & de->vsync_irq) && malidp->crtc.enabled)

		drm_crtc_handle_vblank(&malidp->crtc);

		drm_crtc_handle_vblank(&malidp->crtc);





	malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, status);

	malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, status);

drivers/gpu/drm/arm/malidp_hw.h

+11 −4
Original line number Original line Diff line number Diff line
@@ -58,7 +58,8 @@ struct malidp_layer { 
	u16 id;			/* layer ID */

	u16 id;			/* layer ID */

	u16 base;		/* address offset for the register bank */

	u16 base;		/* address offset for the register bank */

	u16 ptr;		/* address offset for the pointer register */

	u16 ptr;		/* address offset for the pointer register */

	u16 stride_offset;	/* Offset to the first stride register. */

	u16 stride_offset;	/* offset to the first stride register. */

	s16 yuv2rgb_offset;	/* offset to the YUV->RGB matrix entries */

};

};





enum malidp_scaling_coeff_set {

enum malidp_scaling_coeff_set {
@@ -285,10 +286,16 @@ void malidp_se_irq_fini(struct drm_device *drm); 
u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,

u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,

			   u8 layer_id, u32 format);

			   u8 layer_id, u32 format);





static inline bool malidp_hw_pitch_valid(struct malidp_hw_device *hwdev,

static inline u8 malidp_hw_get_pitch_align(struct malidp_hw_device *hwdev, bool rotated)

					 unsigned int pitch)

{

{

	return !(pitch & (hwdev->hw->map.bus_align_bytes - 1));

	/*

	 * only hardware that cannot do 8 bytes bus alignments have further

	 * constraints on rotated planes

	 */

	if (hwdev->hw->map.bus_align_bytes == 8)

		return 8;

	else

		return hwdev->hw->map.bus_align_bytes << (rotated ? 2 : 0);

}

}





/* U16.16 */

/* U16.16 */

CRA Git | Maintained and supported by SUSTech CRA and CCSE