Commit 4f4bc0ab authored Mar 18, 2016 by Andy Shevchenko Committed by Vinod Koul Apr 04, 2016

dmaengine: hsu: correct use of channel status register



There is a typo in documentation regarding to descriptor empty bit (DESCE)
which is set to 1 when descriptor is empty. Thus, status register at the end of
a transfer usually returns all DESCE bits set and thus it will never be zero.

Moreover, there are 2 bits (CDESC) that encode current descriptor, on which
interrupt has been asserted. In case when we have few descriptors programmed we
might have non-zero value.

Remove DESCE and CDESC bits from DMA channel status register (HSU_CH_SR) when
reading it.

Fixes: 2b49e0c5 ("dmaengine: append hsu DMA driver")
Cc: stable@vger.kernel.org
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>

parent a197f3c7

drivers/dma/hsu/hsu.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -135,7 +135,7 @@ static u32 hsu_dma_chan_get_sr(struct hsu_dma_chan *hsuc)
		sr = hsu_chan_readl(hsuc, HSU_CH_SR);
		spin_unlock_irqrestore(&hsuc->vchan.lock, flags);

		return sr;
		return sr & ~(HSU_CH_SR_DESCE_ANY \| HSU_CH_SR_CDESC_ANY);
		}

		irqreturn_t hsu_dma_irq(struct hsu_dma_chip *chip, unsigned short nr)

drivers/dma/hsu/hsu.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -41,6 +41,9 @@
		#define HSU_CH_SR_DESCTO(x) BIT(8 + (x))
		#define HSU_CH_SR_DESCTO_ANY (BIT(11) \| BIT(10) \| BIT(9) \| BIT(8))
		#define HSU_CH_SR_CHE BIT(15)
		#define HSU_CH_SR_DESCE(x) BIT(16 + (x))
		#define HSU_CH_SR_DESCE_ANY (BIT(19) \| BIT(18) \| BIT(17) \| BIT(16))
		#define HSU_CH_SR_CDESC_ANY (BIT(31) \| BIT(30))

		/* Bits in HSU_CH_CR */
		#define HSU_CH_CR_CHA BIT(0)

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