clk: pistachio: Add a pll_lock() helper for clarity (4f4adfbf) · Commits · 戴 / test

drivers/clk/pistachio/clk-pll.c

+8 −4

Original line number	Diff line number	Diff line
		@@ -67,6 +67,12 @@ static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg)
		writel(val, pll->base + reg);
		}

		static inline void pll_lock(struct pistachio_clk_pll *pll)
		{
		while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK))
		cpu_relax();
		}

		static inline u32 do_div_round_closest(u64 dividend, u32 divisor)
		{
		dividend += divisor / 2;
		@@ -178,8 +184,7 @@ static int pll_gf40lp_frac_set_rate(struct clk_hw *hw, unsigned long rate,
		(params->postdiv2 << PLL_FRAC_CTRL2_POSTDIV2_SHIFT);
		pll_writel(pll, val, PLL_CTRL2);

		while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK))
		cpu_relax();
		pll_lock(pll);

		if (!was_enabled)
		pll_gf40lp_frac_disable(hw);
		@@ -288,8 +293,7 @@ static int pll_gf40lp_laint_set_rate(struct clk_hw *hw, unsigned long rate,
		(params->postdiv2 << PLL_INT_CTRL1_POSTDIV2_SHIFT);
		pll_writel(pll, val, PLL_CTRL1);

		while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK))
		cpu_relax();
		pll_lock(pll);

		if (!was_enabled)
		pll_gf40lp_laint_disable(hw);