Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm (4f262acf) · Commits · 戴 / test

arch/arm/Kconfig

+1 −1

Original line number	Diff line number	Diff line
		@@ -1280,7 +1280,7 @@ config ARM_ERRATA_743622
		depends on CPU_V7
		help
		This option enables the workaround for the 743622 Cortex-A9
		(r2p0..r2p2) erratum. Under very rare conditions, a faulty
		(r2p*) erratum. Under very rare conditions, a faulty
		optimisation in the Cortex-A9 Store Buffer may lead to data
		corruption. This workaround sets a specific bit in the diagnostic
		register of the Cortex-A9 which disables the Store Buffer

arch/arm/include/asm/pmu.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -134,7 +134,7 @@ int __init armpmu_register(struct arm_pmu armpmu, char name, int type);

		u64 armpmu_event_update(struct perf_event *event,
		struct hw_perf_event *hwc,
		int idx, int overflow);
		int idx);

		int armpmu_event_set_period(struct perf_event *event,
		struct hw_perf_event *hwc,

arch/arm/kernel/ecard.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -242,6 +242,7 @@ static void ecard_init_pgtables(struct mm_struct *mm)

		memcpy(dst_pgd, src_pgd, sizeof(pgd_t) * (EASI_SIZE / PGDIR_SIZE));

		vma.vm_flags = VM_EXEC;
		vma.vm_mm = mm;

		flush_tlb_range(&vma, IO_START, IO_START + IO_SIZE);

arch/arm/kernel/perf_event.c

+34 −11

Original line number	Diff line number	Diff line
		@@ -180,7 +180,7 @@ armpmu_event_set_period(struct perf_event *event,
		u64
		armpmu_event_update(struct perf_event *event,
		struct hw_perf_event *hwc,
		int idx, int overflow)
		int idx)
		{
		struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
		u64 delta, prev_raw_count, new_raw_count;
		@@ -193,13 +193,7 @@ again:
		new_raw_count) != prev_raw_count)
		goto again;

		new_raw_count &= armpmu->max_period;
		prev_raw_count &= armpmu->max_period;

		if (overflow)
		delta = armpmu->max_period - prev_raw_count + new_raw_count + 1;
		else
		delta = new_raw_count - prev_raw_count;
		delta = (new_raw_count - prev_raw_count) & armpmu->max_period;

		local64_add(delta, &event->count);
		local64_sub(delta, &hwc->period_left);
		@@ -216,7 +210,7 @@ armpmu_read(struct perf_event *event)
		if (hwc->idx < 0)
		return;

		armpmu_event_update(event, hwc, hwc->idx, 0);
		armpmu_event_update(event, hwc, hwc->idx);
		}

		static void
		@@ -232,7 +226,7 @@ armpmu_stop(struct perf_event *event, int flags)
		if (!(hwc->state & PERF_HES_STOPPED)) {
		armpmu->disable(hwc, hwc->idx);
		barrier(); /* why? */
		armpmu_event_update(event, hwc, hwc->idx, 0);
		armpmu_event_update(event, hwc, hwc->idx);
		hwc->state \|= PERF_HES_STOPPED \| PERF_HES_UPTODATE;
		}
		}
		@@ -518,7 +512,13 @@ __hw_perf_event_init(struct perf_event *event)
		hwc->config_base \|= (unsigned long)mapping;

		if (!hwc->sample_period) {
		hwc->sample_period = armpmu->max_period;
		/*
		* For non-sampling runs, limit the sample_period to half
		* of the counter width. That way, the new counter value
		* is far less likely to overtake the previous one unless
		* you have some serious IRQ latency issues.
		*/
		hwc->sample_period = armpmu->max_period >> 1;
		hwc->last_period = hwc->sample_period;
		local64_set(&hwc->period_left, hwc->sample_period);
		}
		@@ -679,6 +679,28 @@ static void __init cpu_pmu_init(struct arm_pmu *armpmu)
		armpmu->type = ARM_PMU_DEVICE_CPU;
		}

		/*
		* PMU hardware loses all context when a CPU goes offline.
		* When a CPU is hotplugged back in, since some hardware registers are
		* UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
		* junk values out of them.
		*/
		static int __cpuinit pmu_cpu_notify(struct notifier_block *b,
		unsigned long action, void *hcpu)
		{
		if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
		return NOTIFY_DONE;

		if (cpu_pmu && cpu_pmu->reset)
		cpu_pmu->reset(NULL);

		return NOTIFY_OK;
		}

		static struct notifier_block __cpuinitdata pmu_cpu_notifier = {
		.notifier_call = pmu_cpu_notify,
		};

		/*
		* CPU PMU identification and registration.
		*/
		@@ -730,6 +752,7 @@ init_hw_perf_events(void)
		pr_info("enabled with %s PMU driver, %d counters available\n",
		cpu_pmu->name, cpu_pmu->num_events);
		cpu_pmu_init(cpu_pmu);
		register_cpu_notifier(&pmu_cpu_notifier);
		armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
		} else {
		pr_info("no hardware support available\n");

arch/arm/kernel/perf_event_v6.c

+3 −19

Original line number	Diff line number	Diff line
		@@ -467,23 +467,6 @@ armv6pmu_enable_event(struct hw_perf_event *hwc,
		raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
		}

		static int counter_is_active(unsigned long pmcr, int idx)
		{
		unsigned long mask = 0;
		if (idx == ARMV6_CYCLE_COUNTER)
		mask = ARMV6_PMCR_CCOUNT_IEN;
		else if (idx == ARMV6_COUNTER0)
		mask = ARMV6_PMCR_COUNT0_IEN;
		else if (idx == ARMV6_COUNTER1)
		mask = ARMV6_PMCR_COUNT1_IEN;

		if (mask)
		return pmcr & mask;

		WARN_ONCE(1, "invalid counter number (%d)\n", idx);
		return 0;
		}

		static irqreturn_t
		armv6pmu_handle_irq(int irq_num,
		void *dev)
		@@ -513,7 +496,8 @@ armv6pmu_handle_irq(int irq_num,
		struct perf_event *event = cpuc->events[idx];
		struct hw_perf_event *hwc;

		if (!counter_is_active(pmcr, idx))
		/* Ignore if we don't have an event. */
		if (!event)
		continue;

		/*
		@@ -524,7 +508,7 @@ armv6pmu_handle_irq(int irq_num,
		continue;

		hwc = &event->hw;
		armpmu_event_update(event, hwc, idx, 1);
		armpmu_event_update(event, hwc, idx);
		data.period = event->hw.last_period;
		if (!armpmu_event_set_period(event, hwc, idx))
		continue;

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