Commit 4efe9b47 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
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drm/amd/pp: Refine code shorten variable name 



Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9bd2bae1

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

+8 −16
Original line number Diff line number Diff line
@@ -1384,11 +1384,9 @@ static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) 
		data->odn_dpm_table.odn_core_clock_dpm_levels.

		number_of_performance_levels = data->dpm_table.gfx_table.count;

		for (i = 0; i < data->dpm_table.gfx_table.count; i++) {

			data->odn_dpm_table.odn_core_clock_dpm_levels.

			performance_level_entries[i].clock =

			data->odn_dpm_table.odn_core_clock_dpm_levels.entries[i].clock =

					data->dpm_table.gfx_table.dpm_levels[i].value;

			data->odn_dpm_table.odn_core_clock_dpm_levels.

			performance_level_entries[i].enabled = true;

			data->odn_dpm_table.odn_core_clock_dpm_levels.entries[i].enabled = true;

		}



		data->odn_dpm_table.vdd_dependency_on_sclk.count =
@@ -1407,11 +1405,9 @@ static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) 
		data->odn_dpm_table.odn_memory_clock_dpm_levels.

		number_of_performance_levels = data->dpm_table.mem_table.count;

		for (i = 0; i < data->dpm_table.mem_table.count; i++) {

			data->odn_dpm_table.odn_memory_clock_dpm_levels.

			performance_level_entries[i].clock =

			data->odn_dpm_table.odn_memory_clock_dpm_levels.entries[i].clock =

					data->dpm_table.mem_table.dpm_levels[i].value;

			data->odn_dpm_table.odn_memory_clock_dpm_levels.

			performance_level_entries[i].enabled = true;

			data->odn_dpm_table.odn_memory_clock_dpm_levels.entries[i].enabled = true;

		}



		data->odn_dpm_table.vdd_dependency_on_mclk.count = dep_mclk_table->count;
@@ -3349,11 +3345,9 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( 
					dpm_count < dpm_table->gfx_table.count;

					dpm_count++) {

				dpm_table->gfx_table.dpm_levels[dpm_count].enabled =

						data->odn_dpm_table.odn_core_clock_dpm_levels.

						performance_level_entries[dpm_count].enabled;

					data->odn_dpm_table.odn_core_clock_dpm_levels.entries[dpm_count].enabled;

				dpm_table->gfx_table.dpm_levels[dpm_count].value =

						data->odn_dpm_table.odn_core_clock_dpm_levels.

						performance_level_entries[dpm_count].clock;

					data->odn_dpm_table.odn_core_clock_dpm_levels.entries[dpm_count].clock;

			}

		}
@@ -3363,11 +3357,9 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( 
					dpm_count < dpm_table->mem_table.count;

					dpm_count++) {

				dpm_table->mem_table.dpm_levels[dpm_count].enabled =

						data->odn_dpm_table.odn_memory_clock_dpm_levels.

						performance_level_entries[dpm_count].enabled;

					data->odn_dpm_table.odn_memory_clock_dpm_levels.entries[dpm_count].enabled;

				dpm_table->mem_table.dpm_levels[dpm_count].value =

						data->odn_dpm_table.odn_memory_clock_dpm_levels.

						performance_level_entries[dpm_count].clock;

					data->odn_dpm_table.odn_memory_clock_dpm_levels.entries[dpm_count].clock;

			}

		}

drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h

+1 −1
Original line number Diff line number Diff line
@@ -370,7 +370,7 @@ struct phm_odn_clock_levels { 
	uint32_t flags;

	uint32_t number_of_performance_levels;

	/* variable-sized array, specify by ulNumberOfPerformanceLevels. */

	struct phm_odn_performance_level performance_level_entries[8];

	struct phm_odn_performance_level entries[8];

};



extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);

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