openrisc: add cacheflush support to fix icache aliasing (4ee93d80) · Commits · 戴 / test

arch/openrisc/Kconfig

+11 −0

Original line number	Diff line number	Diff line
		@@ -77,6 +77,17 @@ config OR1K_1200

		endchoice

		config DCACHE_WRITETHROUGH
		bool "Have write through data caches"
		default n
		help
		Select this if your implementation features write through data caches.
		Selecting 'N' here will allow the kernel to force flushing of data
		caches at relevant times. Most OpenRISC implementations support write-
		through data caches.

		If unsure say N here

		config OPENRISC_BUILTIN_DTB
		string "Builtin DTB"
		default ""

arch/openrisc/include/asm/Kbuild

+0 −1

Original line number	Diff line number	Diff line
		generic-y += barrier.h
		generic-y += bug.h
		generic-y += bugs.h
		generic-y += cacheflush.h
		generic-y += checksum.h
		generic-y += clkdev.h
		generic-y += current.h

arch/openrisc/include/asm/cacheflush.h

0 → 100644

+96 −0

Original line number	Diff line number	Diff line
		/*
		* OpenRISC Linux
		*
		* Linux architectural port borrowing liberally from similar works of
		* others. All original copyrights apply as per the original source
		* declaration.
		*
		* OpenRISC implementation:
		* Copyright (C) Jan Henrik Weinstock <jan.weinstock@rwth-aachen.de>
		* et al.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License as published by
		* the Free Software Foundation; either version 2 of the License, or
		* (at your option) any later version.
		*/

		#ifndef __ASM_CACHEFLUSH_H
		#define __ASM_CACHEFLUSH_H

		#include <linux/mm.h>

		/*
		* Helper function for flushing or invalidating entire pages from data
		* and instruction caches. SMP needs a little extra work, since we need
		* to flush the pages on all cpus.
		*/
		extern void local_dcache_page_flush(struct page *page);
		extern void local_icache_page_inv(struct page *page);

		/*
		* Data cache flushing always happen on the local cpu. Instruction cache
		* invalidations need to be broadcasted to all other cpu in the system in
		* case of SMP configurations.
		*/
		#ifndef CONFIG_SMP
		#define dcache_page_flush(page) local_dcache_page_flush(page)
		#define icache_page_inv(page) local_icache_page_inv(page)
		#else /* CONFIG_SMP */
		#define dcache_page_flush(page) local_dcache_page_flush(page)
		#define icache_page_inv(page) smp_icache_page_inv(page)
		extern void smp_icache_page_inv(struct page *page);
		#endif /* CONFIG_SMP */

		/*
		* Synchronizes caches. Whenever a cpu writes executable code to memory, this
		* should be called to make sure the processor sees the newly written code.
		*/
		static inline void sync_icache_dcache(struct page *page)
		{
		if (!IS_ENABLED(CONFIG_DCACHE_WRITETHROUGH))
		dcache_page_flush(page);
		icache_page_inv(page);
		}

		/*
		* Pages with this bit set need not be flushed/invalidated, since
		* they have not changed since last flush. New pages start with
		* PG_arch_1 not set and are therefore dirty by default.
		*/
		#define PG_dc_clean PG_arch_1

		#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
		static inline void flush_dcache_page(struct page *page)
		{
		clear_bit(PG_dc_clean, &page->flags);
		}

		/*
		* Other interfaces are not required since we do not have virtually
		* indexed or tagged caches. So we can use the default here.
		*/
		#define flush_cache_all() do { } while (0)
		#define flush_cache_mm(mm) do { } while (0)
		#define flush_cache_dup_mm(mm) do { } while (0)
		#define flush_cache_range(vma, start, end) do { } while (0)
		#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
		#define flush_dcache_mmap_lock(mapping) do { } while (0)
		#define flush_dcache_mmap_unlock(mapping) do { } while (0)
		#define flush_icache_range(start, end) do { } while (0)
		#define flush_icache_page(vma, pg) do { } while (0)
		#define flush_icache_user_range(vma, pg, adr, len) do { } while (0)
		#define flush_cache_vmap(start, end) do { } while (0)
		#define flush_cache_vunmap(start, end) do { } while (0)

		#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
		do { \
		memcpy(dst, src, len); \
		if (vma->vm_flags & VM_EXEC) \
		sync_icache_dcache(page); \
		} while (0)

		#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
		memcpy(dst, src, len)

		#endif /* __ASM_CACHEFLUSH_H */

arch/openrisc/include/asm/pgtable.h

+10 −6

Original line number	Diff line number	Diff line
		@@ -416,15 +416,19 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */

		struct vm_area_struct;

		/*
		* or32 doesn't have any external MMU info: the kernel page
		* tables contain all the necessary information.
		*
		* Actually I am not sure on what this could be used for.
		*/
		static inline void update_tlb(struct vm_area_struct *vma,
		unsigned long address, pte_t *pte)
		{
		}

		extern void update_cache(struct vm_area_struct *vma,
		unsigned long address, pte_t *pte);

		static inline void update_mmu_cache(struct vm_area_struct *vma,
		unsigned long address, pte_t *pte)
		{
		update_tlb(vma, address, pte);
		update_cache(vma, address, pte);
		}

		/* __PHX__ FIXME, SWAP, this probably doesn't work */

arch/openrisc/kernel/smp.c

+15 −0

Original line number	Diff line number	Diff line
		@@ -18,6 +18,7 @@
		#include <asm/cpuinfo.h>
		#include <asm/mmu_context.h>
		#include <asm/tlbflush.h>
		#include <asm/cacheflush.h>
		#include <asm/time.h>

		static void (smp_cross_call)(const struct cpumask , unsigned int);
		@@ -239,3 +240,17 @@ void flush_tlb_range(struct vm_area_struct *vma,
		{
		on_each_cpu(ipi_flush_tlb_all, NULL, 1);
		}

		/* Instruction cache invalidate - performed on each cpu */
		static void ipi_icache_page_inv(void *arg)
		{
		struct page *page = arg;

		local_icache_page_inv(page);
		}

		void smp_icache_page_inv(struct page *page)
		{
		on_each_cpu(ipi_icache_page_inv, page, 1);
		}
		EXPORT_SYMBOL(smp_icache_page_inv);

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