Commit 4ee48627 authored Dec 02, 2014 by Markos Chandras

MIPS: mm: c-r4k: Set the correct ISA level



The local_r4k_flush_cache_sigtramp function uses the 'cache'
instruction inside an asm block. However, MIPS R6 changed the
opcode for the cache instruction and as a result of which we
need to set the correct ISA level.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

parent 77f3ee59

arch/mips/mm/c-r4k.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -794,7 +794,7 @@ static void local_r4k_flush_cache_sigtramp(void * arg)
		__asm__ __volatile__ (
		".set push\n\t"
		".set noat\n\t"
		".set mips3\n\t"
		".set "MIPS_ISA_LEVEL"\n\t"
		#ifdef CONFIG_32BIT
		"la $at,1f\n\t"
		#endif

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