Commit 4edbe6aa authored by Fabio Estevam's avatar Fabio Estevam Committed by Shawn Guo
Browse files

ARM: dts: imx7d-pico-pi: Move SoM related part to imx7d-pico.dtsi 



imx7d-pico-pi board contains:

- One SoM board (imx7d pico)
- One base board (pi).

In order to make it easier for adding support for other board variants,
move the commom SoM part to the imx7d-pico.dtsi file.

Signed-off-by: default avatarFabio Estevam <festevam@gmail.com>
Signed-off-by: default avatarOtavio Salvador <otavio@ossystems.com.br>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent a26aec53

arch/arm/boot/dts/imx7d-pico-pi.dts

+5 −111
Original line number Diff line number Diff line
@@ -5,6 +5,9 @@ 
#include "imx7d-pico.dtsi"



/ {

	model = "TechNexion PICO-IMX7D Board and PI baseboard";

	compatible = "technexion,imx7d-pico-pi", "fsl,imx7d";



	sound {

		compatible = "simple-audio-card";

		simple-audio-card,name = "imx7-sgtl5000";
@@ -16,43 +19,14 @@ 
		};



		dailink_master: simple-audio-card,codec {

			sound-dai = <&codec>;

			sound-dai = <&sgtl5000>;

			clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;

		};

	};

};



&fec1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enet1>;

	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,

			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;

	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;

	assigned-clock-rates = <0>, <100000000>;

	phy-mode = "rgmii";

	phy-handle = <&ethphy0>;

	fsl,magic-packet;

	status = "okay";



	mdio {

		#address-cells = <1>;

		#size-cells = <0>;



		ethphy0: ethernet-phy@1 {

			compatible = "ethernet-phy-ieee802.3-c22";

			reg = <1>;

			status = "okay";

		};

	};

};



&i2c1 {

	clock-frequency = <100000>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_i2c1>;

	status = "okay";



	codec: sgtl5000@a {

	sgtl5000: codec@a {

		#sound-dai-cells = <0>;

		reg = <0x0a>;

		compatible = "fsl,sgtl5000";
@@ -61,83 +35,3 @@ 
		VDDIO-supply = <&reg_vref_1v8>;

	};

};
 




&sai1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_sai1>;

	assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,

			  <&clks IMX7D_SAI1_ROOT_CLK>;

	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;

	assigned-clock-rates = <0>, <24576000>;

	status = "okay";

};



&uart5 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart5>;

	assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;

	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;

	status = "okay";

};



&usbotg1 {

	vbus-supply = <&reg_usb_otg1_vbus>;

	status = "okay";

};



&usbotg2 {

	vbus-supply = <&reg_usb_otg2_vbus>;

	dr_mode = "host";

	status = "okay";

};



&iomuxc {

	pinctrl_enet1: enet1grp {

		fsl,pins = <

			MX7D_PAD_SD2_CD_B__ENET1_MDIO			0x3

			MX7D_PAD_SD2_WP__ENET1_MDC			0x3

			MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x1

			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x1

			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x1

			MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x1

			MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x1

			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x1

			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x1

			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x1

			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x1

			MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x1

			MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x1

			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x1

		>;

	};



	pinctrl_i2c1: i2c1grp {

		fsl,pins = <

			MX7D_PAD_UART1_TX_DATA__I2C1_SDA	0x4000007f

			MX7D_PAD_UART1_RX_DATA__I2C1_SCL	0x4000007f

		>;

	};



	pinctrl_sai1: sai1grp {

		fsl,pins = <

			MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK	0x1f

			MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC	0x1f

			MX7D_PAD_ENET1_COL__SAI1_TX_DATA0	0x30

			MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0	0x1f

		>;

	};



	pinctrl_uart5: uart5grp {

		fsl,pins = <

			MX7D_PAD_I2C4_SDA__UART5_DCE_TX		0x79

			MX7D_PAD_I2C4_SCL__UART5_DCE_RX		0x79

		>;

	};



	pinctrl_usbotg1_pwr: usbotg_pwr {

		fsl,pins = <

			MX7D_PAD_UART3_TX_DATA__GPIO4_IO5	0x14

		>;

	};

};

arch/arm/boot/dts/imx7d-pico.dtsi

+108 −3
Original line number Diff line number Diff line
@@ -7,9 +7,6 @@ 
#include "imx7d.dtsi"



/ {

	model = "Technexion Pico i.MX7D Board";

	compatible = "technexion,imx7d-pico", "fsl,imx7d";



	/* Will be filled by the bootloader */

	memory@80000000 {

		device_type = "memory";
@@ -79,6 +76,37 @@ 
	assigned-clock-rates = <0>, <32768>;

};



&fec1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enet1>;

	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,

			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;

	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;

	assigned-clock-rates = <0>, <100000000>;

	phy-mode = "rgmii";

	phy-handle = <&ethphy0>;

	fsl,magic-packet;

	status = "okay";



	mdio {

		#address-cells = <1>;

		#size-cells = <0>;



		ethphy0: ethernet-phy@1 {

			compatible = "ethernet-phy-ieee802.3-c22";

			reg = <1>;

			status = "okay";

		};

	};

};



&i2c1 {

	clock-frequency = <100000>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_i2c1>;

	status = "okay";

};



&i2c4 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_i2c4>;
@@ -174,6 +202,35 @@ 
	};

};



&sai1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_sai1>;

	assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,

			  <&clks IMX7D_SAI1_ROOT_CLK>;

	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;

	assigned-clock-rates = <0>, <24576000>;

	status = "okay";

};



&uart5 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart5>;

	assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;

	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;

	status = "okay";

};



&usbotg1 {

	vbus-supply = <&reg_usb_otg1_vbus>;

	status = "okay";

};



&usbotg2 {

	vbus-supply = <&reg_usb_otg2_vbus>;

	dr_mode = "host";

	status = "okay";

};



&usdhc2 { /* Wifi SDIO */

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>;
@@ -208,6 +265,32 @@ 
};



&iomuxc {

	pinctrl_i2c1: i2c1grp {

		fsl,pins = <

			MX7D_PAD_UART1_TX_DATA__I2C1_SDA	0x4000007f

			MX7D_PAD_UART1_RX_DATA__I2C1_SCL	0x4000007f

		>;

	};



	pinctrl_enet1: enet1grp {

		fsl,pins = <

			MX7D_PAD_SD2_CD_B__ENET1_MDIO			0x3

			MX7D_PAD_SD2_WP__ENET1_MDC			0x3

			MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x1

			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x1

			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x1

			MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x1

			MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x1

			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x1

			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x1

			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x1

			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x1

			MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x1

			MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x1

			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x1

		>;

	};



	pinctrl_i2c4: i2c4grp {

		fsl,pins = <

			MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA		0x4000007f
@@ -221,6 +304,28 @@ 
		>;

	};



	pinctrl_sai1: sai1grp {

		fsl,pins = <

			MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK	0x1f

			MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC	0x1f

			MX7D_PAD_ENET1_COL__SAI1_TX_DATA0	0x30

			MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0	0x1f

		>;

	};



	pinctrl_uart5: uart5grp {

		fsl,pins = <

			MX7D_PAD_I2C4_SDA__UART5_DCE_TX		0x79

			MX7D_PAD_I2C4_SCL__UART5_DCE_RX		0x79

		>;

	};



	pinctrl_usbotg1_pwr: usbotg_pwr {

		fsl,pins = <

			MX7D_PAD_UART3_TX_DATA__GPIO4_IO5	0x14

		>;

	};



	pinctrl_usdhc2: usdhc2grp {

		fsl,pins = <

			MX7D_PAD_SD2_CMD__SD2_CMD		0x59

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