Commit 4ed7e4e5 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'ti-k3-soc-for-v5.3' of... 

Merge tag 'ti-k3-soc-for-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into arm/dt

Texas Instruments K3 SoC family changes for 5.3

- Add support for the new J721e SoC, includes basic peripherals needed for
  booting up the device
- New peripheral support added for AM654x:
  * TI SCI irqchip
  * GPIO
  * MCU SRAM
  * R5Fs
  * MSMC RAM
  * SERDES and PCIe

* tag 'ti-k3-soc-for-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux

: (26 commits)
  arm64: dts: ti: k3-j721e: Add the MCU SRAM node
  arm64: dts: ti: k3-j721e: Add interrupt controllers in wakeup domain
  arm64: dts: ti: k3-j721e: Add interrupt controllers in main domain
  arm64: dts: ti: k3-j721e-main: Add Main NavSS Interrupt controller node
  arm64: defconfig: Enable TI's J721E SoC platform
  arm64: dts: ti: Add support for J721E Common Processor Board
  soc: ti: Add Support for J721E SoC config option
  arm64: dts: ti: Add Support for J721E SoC
  dt-bindings: serial: 8250_omap: Add compatible for J721E UART controller
  dt-bindings: arm: ti: Add bindings for J721E SoC
  arm64: dts: ti: am654-base-board: Disable SERDES and PCIe
  arm64: dts: k3-am6: Add PCIe Endpoint DT node
  arm64: dts: k3-am6: Add PCIe Root Complex DT node
  arm64: dts: k3-am6: Add SERDES DT node
  arm64: dts: k3-am6: Add mux-controller DT node required for muxing SERDES
  arm64: dts: k3-am6: Add "socionext,synquacer-pre-its" property to gic_its
  arm64: dts: ti: k3-am65: Add MSMC RAM ranges in interconnect node
  arm64: dts: ti: k3-am65: Add R5F ranges in interconnect nodes
  arm64: dts: ti: k3-am65-mcu: Add the MCU RAM node
  arm64: dts: ti: k3-am65: Add MCU SRAM ranges in interconnect nodes
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 50f5ef46 78eccc2a

Documentation/devicetree/bindings/arm/ti/k3.txt

+3 −0
Original line number Diff line number Diff line
@@ -13,6 +13,9 @@ architecture it uses, using one of the following compatible values: 
- AM654

  compatible = "ti,am654";



- J721E

  compatible = "ti,j721e";



Boards

------

Documentation/devicetree/bindings/serial/omap_serial.txt

+1 −0
Original line number Diff line number Diff line 
OMAP UART controller



Required properties:

- compatible : should be "ti,j721e-uart", "ti,am654-uart" for J721E controllers

- compatible : should be "ti,am654-uart" for AM654 controllers

- compatible : should be "ti,omap2-uart" for OMAP2 controllers

- compatible : should be "ti,omap3-uart" for OMAP3 controllers

arch/arm64/boot/dts/ti/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -7,3 +7,5 @@ 
#



dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am654-base-board.dtb



dtb-$(CONFIG_ARCH_K3_J721E_SOC) += k3-j721e-common-proc-board.dtb

arch/arm64/boot/dts/ti/k3-am65-main.dtsi

+201 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
 *

 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/

 */

#include <dt-bindings/phy/phy-am654-serdes.h>



&cbass_main {

	msmc_ram: sram@70000000 {
@@ -44,6 +45,7 @@ 
		gic_its: gic-its@18200000 {

			compatible = "arm,gic-v3-its";

			reg = <0x00 0x01820000 0x00 0x10000>;

			socionext,synquacer-pre-its = <0x1000000 0x400000>;

			msi-controller;

			#msi-cells = <1>;

		};
@@ -60,6 +62,36 @@ 
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

	};



	serdes0: serdes@900000 {

		compatible = "ti,phy-am654-serdes";

		reg = <0x0 0x900000 0x0 0x2000>;

		reg-names = "serdes";

		#phy-cells = <2>;

		power-domains = <&k3_pds 153>;

		clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;

		clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";

		assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;

		assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;

		ti,serdes-clk = <&serdes0_clk>;

		#clock-cells = <1>;

		mux-controls = <&serdes_mux 0>;

	};



	serdes1: serdes@910000 {

		compatible = "ti,phy-am654-serdes";

		reg = <0x0 0x910000 0x0 0x2000>;

		reg-names = "serdes";

		#phy-cells = <2>;

		power-domains = <&k3_pds 154>;

		clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;

		clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";

		assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;

		assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;

		ti,serdes-clk = <&serdes1_clk>;

		#clock-cells = <1>;

		mux-controls = <&serdes_mux 1>;

	};



	main_uart0: serial@2800000 {

		compatible = "ti,am654-uart";

		reg = <0x00 0x02800000 0x00 0x100>;
@@ -232,6 +264,38 @@ 
		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0x0 0x00100000 0x1c000>;



		pcie0_mode: pcie-mode@4060 {

			compatible = "syscon";

			reg = <0x00004060 0x4>;

		};



		pcie1_mode: pcie-mode@4070 {

			compatible = "syscon";

			reg = <0x00004070 0x4>;

		};



		pcie_devid: pcie-devid@210 {

			compatible = "syscon";

			reg = <0x00000210 0x4>;

		};



		serdes0_clk: serdes_clk@4080 {

			compatible = "syscon";

			reg = <0x00004080 0x4>;

		};



		serdes1_clk: serdes_clk@4090 {

			compatible = "syscon";

			reg = <0x00004090 0x4>;

		};



		serdes_mux: mux-controller {

			compatible = "mmio-mux";

			#mux-control-cells = <1>;

			mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */

					<0x4090 0x3>; /* SERDES1 lane select */

		};

	};



	dwc3_0: dwc3@4000000 {
@@ -309,4 +373,141 @@ 
		clock-names = "wkupclk", "refclk";

		#phy-cells = <0>;

	};



	intr_main_gpio: interrupt-controller0 {

		compatible = "ti,sci-intr";

		ti,intr-trigger-type = <1>;

		interrupt-controller;

		interrupt-parent = <&gic500>;

		#interrupt-cells = <2>;

		ti,sci = <&dmsc>;

		ti,sci-dst-id = <56>;

		ti,sci-rm-range-girq = <0x1>;

	};



	cbass_main_navss: interconnect0 {

		compatible = "simple-bus";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		intr_main_navss: interrupt-controller1 {

			compatible = "ti,sci-intr";

			ti,intr-trigger-type = <4>;

			interrupt-controller;

			interrupt-parent = <&gic500>;

			#interrupt-cells = <2>;

			ti,sci = <&dmsc>;

			ti,sci-dst-id = <56>;

			ti,sci-rm-range-girq = <0x0>, <0x2>;

		};



		inta_main_udmass: interrupt-controller@33d00000 {

			compatible = "ti,sci-inta";

			reg = <0x0 0x33d00000 0x0 0x100000>;

			interrupt-controller;

			interrupt-parent = <&intr_main_navss>;

			msi-controller;

			ti,sci = <&dmsc>;

			ti,sci-dev-id = <179>;

			ti,sci-rm-range-vint = <0x0>;

			ti,sci-rm-range-global-event = <0x1>;

		};

	};



	main_gpio0:  main_gpio0@600000 {

		compatible = "ti,am654-gpio", "ti,keystone-gpio";

		reg = <0x0 0x600000 0x0 0x100>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-parent = <&intr_main_gpio>;

		interrupts = <57 256>, <57 257>, <57 258>, <57 259>, <57 260>,

				<57 261>;

		interrupt-controller;

		#interrupt-cells = <2>;

		ti,ngpio = <96>;

		ti,davinci-gpio-unbanked = <0>;

		clocks = <&k3_clks 57 0>;

		clock-names = "gpio";

	};



	main_gpio1:  main_gpio1@601000 {

		compatible = "ti,am654-gpio", "ti,keystone-gpio";

		reg = <0x0 0x601000 0x0 0x100>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-parent = <&intr_main_gpio>;

		interrupts = <58 256>, <58 257>, <58 258>, <58 259>, <58 260>,

				<58 261>;

		interrupt-controller;

		#interrupt-cells = <2>;

		ti,ngpio = <90>;

		ti,davinci-gpio-unbanked = <0>;

		clocks = <&k3_clks 58 0>;

		clock-names = "gpio";

	};



	pcie0_rc: pcie@5500000 {

		compatible = "ti,am654-pcie-rc";

		reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;

		reg-names = "app", "dbics", "config", "atu";

		power-domains = <&k3_pds 120>;

		#address-cells = <3>;

		#size-cells = <2>;

		ranges = <0x81000000 0 0          0x0 0x10020000 0 0x00010000

			  0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;

		ti,syscon-pcie-id = <&pcie_devid>;

		ti,syscon-pcie-mode = <&pcie0_mode>;

		bus-range = <0x0 0xff>;

		num-viewport = <16>;

		max-link-speed = <3>;

		dma-coherent;

		interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;

		msi-map = <0x0 &gic_its 0x0 0x10000>;

	};



	pcie0_ep: pcie-ep@5500000 {

		compatible = "ti,am654-pcie-ep";

		reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;

		reg-names = "app", "dbics", "addr_space", "atu";

		power-domains = <&k3_pds 120>;

		ti,syscon-pcie-mode = <&pcie0_mode>;

		num-ib-windows = <16>;

		num-ob-windows = <16>;

		max-link-speed = <3>;

		dma-coherent;

		interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;

	};



	pcie1_rc: pcie@5600000 {

		compatible = "ti,am654-pcie-rc";

		reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;

		reg-names = "app", "dbics", "config", "atu";

		power-domains = <&k3_pds 121>;

		#address-cells = <3>;

		#size-cells = <2>;

		ranges = <0x81000000 0 0          0x0   0x18020000 0 0x00010000

			  0x82000000 0 0x18030000 0x0   0x18030000 0 0x07FD0000>;

		ti,syscon-pcie-id = <&pcie_devid>;

		ti,syscon-pcie-mode = <&pcie1_mode>;

		bus-range = <0x0 0xff>;

		num-viewport = <16>;

		max-link-speed = <3>;

		dma-coherent;

		interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;

		msi-map = <0x0 &gic_its 0x10000 0x10000>;

	};



	pcie1_ep: pcie-ep@5600000 {

		compatible = "ti,am654-pcie-ep";

		reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;

		reg-names = "app", "dbics", "addr_space", "atu";

		power-domains = <&k3_pds 121>;

		ti,syscon-pcie-mode = <&pcie1_mode>;

		num-ib-windows = <16>;

		num-ob-windows = <16>;

		max-link-speed = <3>;

		dma-coherent;

		interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;

	};

};

arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -17,6 +17,14 @@ 
			power-domains = <&k3_pds 149>;

	};



	mcu_ram: sram@41c00000 {

		compatible = "mmio-sram";

		reg = <0x00 0x41c00000 0x00 0x80000>;

		ranges = <0x0 0x00 0x41c00000 0x80000>;

		#address-cells = <1>;

		#size-cells = <1>;

	};



	mcu_i2c0: i2c@40b00000 {

		compatible = "ti,am654-i2c", "ti,omap4-i2c";

		reg = <0x0 0x40b00000 0x0 0x100>;

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