Commit 4ed39004 authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
Browse files

Merge branch 'pm-cpufreq' 

* pm-cpufreq: (94 commits)
  intel_pstate: Do not skip samples partially
  intel_pstate: Remove freq calculation from intel_pstate_calc_busy()
  intel_pstate: Move intel_pstate_calc_busy() into get_target_pstate_use_performance()
  intel_pstate: Optimize calculation for max/min_perf_adj
  intel_pstate: Remove extra conversions in pid calculation
  cpufreq: Move scheduler-related code to the sched directory
  Revert "cpufreq: postfix policy directory with the first CPU in related_cpus"
  cpufreq: Reduce cpufreq_update_util() overhead a bit
  cpufreq: Select IRQ_WORK if CPU_FREQ_GOV_COMMON is set
  cpufreq: Remove 'policy->governor_enabled'
  cpufreq: Rename __cpufreq_governor() to cpufreq_governor()
  cpufreq: Relocate handle_update() to kill its declaration
  cpufreq: governor: Drop unnecessary checks from show() and store()
  cpufreq: governor: Fix race in dbs_update_util_handler()
  cpufreq: governor: Make gov_set_update_util() static
  cpufreq: governor: Narrow down the dbs_data_mutex coverage
  cpufreq: governor: Make dbs_data_mutex static
  cpufreq: governor: Relocate definitions of tuners structures
  cpufreq: governor: Move per-CPU data to the common code
  cpufreq: governor: Make governor private data per-policy
  ...
parents b5d5fad9 4fec7ad5

Documentation/cpu-freq/intel-pstate.txt

+1 −1
Original line number Diff line number Diff line
@@ -25,7 +25,7 @@ callback, so cpufreq core can't request a transition to a specific frequency. 
The driver provides minimum and maximum frequency limits and callbacks to set a

policy. The policy in cpufreq sysfs is referred to as the "scaling governor".

The cpufreq core can request the driver to operate in any of the two policies:

"performance: and "powersave". The driver decides which frequency to use based

"performance" and "powersave". The driver decides which frequency to use based

on the above policy selection considering minimum and maximum frequency limits.



The Intel P-State driver falls under the latter category, which implements the

drivers/cpufreq/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ config CPU_FREQ 
if CPU_FREQ



config CPU_FREQ_GOV_COMMON

	select IRQ_WORK

	bool



config CPU_FREQ_BOOST_SW

drivers/cpufreq/acpi-cpufreq.c

+96 −116
Original line number Diff line number Diff line
@@ -70,6 +70,8 @@ struct acpi_cpufreq_data { 
	unsigned int cpu_feature;

	unsigned int acpi_perf_cpu;

	cpumask_var_t freqdomain_cpus;

	void (*cpu_freq_write)(struct acpi_pct_register *reg, u32 val);

	u32 (*cpu_freq_read)(struct acpi_pct_register *reg);

};



/* acpi_perf_data is a pointer to percpu data. */
@@ -243,125 +245,119 @@ static unsigned extract_freq(u32 val, struct acpi_cpufreq_data *data) 
	}

}



struct msr_addr {

	u32 reg;

};

u32 cpu_freq_read_intel(struct acpi_pct_register *not_used)

{

	u32 val, dummy;



struct io_addr {

	u16 port;

	u8 bit_width;

};

	rdmsr(MSR_IA32_PERF_CTL, val, dummy);

	return val;

}



void cpu_freq_write_intel(struct acpi_pct_register *not_used, u32 val)

{

	u32 lo, hi;



	rdmsr(MSR_IA32_PERF_CTL, lo, hi);

	lo = (lo & ~INTEL_MSR_RANGE) | (val & INTEL_MSR_RANGE);

	wrmsr(MSR_IA32_PERF_CTL, lo, hi);

}



u32 cpu_freq_read_amd(struct acpi_pct_register *not_used)

{

	u32 val, dummy;



	rdmsr(MSR_AMD_PERF_CTL, val, dummy);

	return val;

}



void cpu_freq_write_amd(struct acpi_pct_register *not_used, u32 val)

{

	wrmsr(MSR_AMD_PERF_CTL, val, 0);

}



u32 cpu_freq_read_io(struct acpi_pct_register *reg)

{

	u32 val;



	acpi_os_read_port(reg->address, &val, reg->bit_width);

	return val;

}



void cpu_freq_write_io(struct acpi_pct_register *reg, u32 val)

{

	acpi_os_write_port(reg->address, val, reg->bit_width);

}



struct drv_cmd {

	unsigned int type;

	const struct cpumask *mask;

	union {

		struct msr_addr msr;

		struct io_addr io;

	} addr;

	struct acpi_pct_register *reg;

	u32 val;

	union {

		void (*write)(struct acpi_pct_register *reg, u32 val);

		u32 (*read)(struct acpi_pct_register *reg);

	} func;

};



/* Called via smp_call_function_single(), on the target CPU */

static void do_drv_read(void *_cmd)

{

	struct drv_cmd *cmd = _cmd;

	u32 h;



	switch (cmd->type) {

	case SYSTEM_INTEL_MSR_CAPABLE:

	case SYSTEM_AMD_MSR_CAPABLE:

		rdmsr(cmd->addr.msr.reg, cmd->val, h);

		break;

	case SYSTEM_IO_CAPABLE:

		acpi_os_read_port((acpi_io_address)cmd->addr.io.port,

				&cmd->val,

				(u32)cmd->addr.io.bit_width);

		break;

	default:

		break;

	}

	cmd->val = cmd->func.read(cmd->reg);

}



/* Called via smp_call_function_many(), on the target CPUs */

static void do_drv_write(void *_cmd)

static u32 drv_read(struct acpi_cpufreq_data *data, const struct cpumask *mask)

{

	struct drv_cmd *cmd = _cmd;

	u32 lo, hi;

	struct acpi_processor_performance *perf = to_perf_data(data);

	struct drv_cmd cmd = {

		.reg = &perf->control_register,

		.func.read = data->cpu_freq_read,

	};

	int err;



	switch (cmd->type) {

	case SYSTEM_INTEL_MSR_CAPABLE:

		rdmsr(cmd->addr.msr.reg, lo, hi);

		lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE);

		wrmsr(cmd->addr.msr.reg, lo, hi);

		break;

	case SYSTEM_AMD_MSR_CAPABLE:

		wrmsr(cmd->addr.msr.reg, cmd->val, 0);

		break;

	case SYSTEM_IO_CAPABLE:

		acpi_os_write_port((acpi_io_address)cmd->addr.io.port,

				cmd->val,

				(u32)cmd->addr.io.bit_width);

		break;

	default:

		break;

	}

	err = smp_call_function_any(mask, do_drv_read, &cmd, 1);

	WARN_ON_ONCE(err);	/* smp_call_function_any() was buggy? */

	return cmd.val;

}



static void drv_read(struct drv_cmd *cmd)

/* Called via smp_call_function_many(), on the target CPUs */

static void do_drv_write(void *_cmd)

{

	int err;

	cmd->val = 0;

	struct drv_cmd *cmd = _cmd;



	err = smp_call_function_any(cmd->mask, do_drv_read, cmd, 1);

	WARN_ON_ONCE(err);	/* smp_call_function_any() was buggy? */

	cmd->func.write(cmd->reg, cmd->val);

}



static void drv_write(struct drv_cmd *cmd)

static void drv_write(struct acpi_cpufreq_data *data,

		      const struct cpumask *mask, u32 val)

{

	struct acpi_processor_performance *perf = to_perf_data(data);

	struct drv_cmd cmd = {

		.reg = &perf->control_register,

		.val = val,

		.func.write = data->cpu_freq_write,

	};

	int this_cpu;



	this_cpu = get_cpu();

	if (cpumask_test_cpu(this_cpu, cmd->mask))

		do_drv_write(cmd);

	smp_call_function_many(cmd->mask, do_drv_write, cmd, 1);

	if (cpumask_test_cpu(this_cpu, mask))

		do_drv_write(&cmd);



	smp_call_function_many(mask, do_drv_write, &cmd, 1);

	put_cpu();

}



static u32

get_cur_val(const struct cpumask *mask, struct acpi_cpufreq_data *data)

static u32 get_cur_val(const struct cpumask *mask, struct acpi_cpufreq_data *data)

{

	struct acpi_processor_performance *perf;

	struct drv_cmd cmd;

	u32 val;



	if (unlikely(cpumask_empty(mask)))

		return 0;



	switch (data->cpu_feature) {

	case SYSTEM_INTEL_MSR_CAPABLE:

		cmd.type = SYSTEM_INTEL_MSR_CAPABLE;

		cmd.addr.msr.reg = MSR_IA32_PERF_CTL;

		break;

	case SYSTEM_AMD_MSR_CAPABLE:

		cmd.type = SYSTEM_AMD_MSR_CAPABLE;

		cmd.addr.msr.reg = MSR_AMD_PERF_CTL;

		break;

	case SYSTEM_IO_CAPABLE:

		cmd.type = SYSTEM_IO_CAPABLE;

		perf = to_perf_data(data);

		cmd.addr.io.port = perf->control_register.address;

		cmd.addr.io.bit_width = perf->control_register.bit_width;

		break;

	default:

		return 0;

	}



	cmd.mask = mask;

	drv_read(&cmd);

	val = drv_read(data, mask);



	pr_debug("get_cur_val = %u\n", cmd.val);

	pr_debug("get_cur_val = %u\n", val);



	return cmd.val;

	return val;

}



static unsigned int get_cur_freq_on_cpu(unsigned int cpu)
@@ -416,7 +412,7 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy, 
{

	struct acpi_cpufreq_data *data = policy->driver_data;

	struct acpi_processor_performance *perf;

	struct drv_cmd cmd;

	const struct cpumask *mask;

	unsigned int next_perf_state = 0; /* Index into perf table */

	int result = 0;
@@ -434,42 +430,21 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy, 
		} else {

			pr_debug("Already at target state (P%d)\n",

				next_perf_state);

			goto out;

		}

			return 0;

		}



	switch (data->cpu_feature) {

	case SYSTEM_INTEL_MSR_CAPABLE:

		cmd.type = SYSTEM_INTEL_MSR_CAPABLE;

		cmd.addr.msr.reg = MSR_IA32_PERF_CTL;

		cmd.val = (u32) perf->states[next_perf_state].control;

		break;

	case SYSTEM_AMD_MSR_CAPABLE:

		cmd.type = SYSTEM_AMD_MSR_CAPABLE;

		cmd.addr.msr.reg = MSR_AMD_PERF_CTL;

		cmd.val = (u32) perf->states[next_perf_state].control;

		break;

	case SYSTEM_IO_CAPABLE:

		cmd.type = SYSTEM_IO_CAPABLE;

		cmd.addr.io.port = perf->control_register.address;

		cmd.addr.io.bit_width = perf->control_register.bit_width;

		cmd.val = (u32) perf->states[next_perf_state].control;

		break;

	default:

		result = -ENODEV;

		goto out;

	}



	/* cpufreq holds the hotplug lock, so we are safe from here on */

	if (policy->shared_type != CPUFREQ_SHARED_TYPE_ANY)

		cmd.mask = policy->cpus;

	else

		cmd.mask = cpumask_of(policy->cpu);

	/*

	 * The core won't allow CPUs to go away until the governor has been

	 * stopped, so we can rely on the stability of policy->cpus.

	 */

	mask = policy->shared_type == CPUFREQ_SHARED_TYPE_ANY ?

		cpumask_of(policy->cpu) : policy->cpus;



	drv_write(&cmd);

	drv_write(data, mask, perf->states[next_perf_state].control);



	if (acpi_pstate_strict) {

		if (!check_freqs(cmd.mask, data->freq_table[index].frequency,

		if (!check_freqs(mask, data->freq_table[index].frequency,

					data)) {

			pr_debug("acpi_cpufreq_target failed (%d)\n",

				policy->cpu);
@@ -480,7 +455,6 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy, 
	if (!result)

		perf->state = next_perf_state;



out:

	return result;

}
@@ -740,15 +714,21 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) 
		}

		pr_debug("SYSTEM IO addr space\n");

		data->cpu_feature = SYSTEM_IO_CAPABLE;

		data->cpu_freq_read = cpu_freq_read_io;

		data->cpu_freq_write = cpu_freq_write_io;

		break;

	case ACPI_ADR_SPACE_FIXED_HARDWARE:

		pr_debug("HARDWARE addr space\n");

		if (check_est_cpu(cpu)) {

			data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE;

			data->cpu_freq_read = cpu_freq_read_intel;

			data->cpu_freq_write = cpu_freq_write_intel;

			break;

		}

		if (check_amd_hwpstate_cpu(cpu)) {

			data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE;

			data->cpu_freq_read = cpu_freq_read_amd;

			data->cpu_freq_write = cpu_freq_write_amd;

			break;

		}

		result = -ENODEV;

drivers/cpufreq/amd_freq_sensitivity.c

+4 −4
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ 
#include <asm/msr.h>

#include <asm/cpufeature.h>



#include "cpufreq_governor.h"

#include "cpufreq_ondemand.h"



#define MSR_AMD64_FREQ_SENSITIVITY_ACTUAL	0xc0010080

#define MSR_AMD64_FREQ_SENSITIVITY_REFERENCE	0xc0010081
@@ -45,10 +45,10 @@ static unsigned int amd_powersave_bias_target(struct cpufreq_policy *policy, 
	long d_actual, d_reference;

	struct msr actual, reference;

	struct cpu_data_t *data = &per_cpu(cpu_data, policy->cpu);

	struct dbs_data *od_data = policy->governor_data;

	struct policy_dbs_info *policy_dbs = policy->governor_data;

	struct dbs_data *od_data = policy_dbs->dbs_data;

	struct od_dbs_tuners *od_tuners = od_data->tuners;

	struct od_cpu_dbs_info_s *od_info =

		od_data->cdata->get_cpu_dbs_info_s(policy->cpu);

	struct od_policy_dbs_info *od_info = to_dbs_info(policy_dbs);



	if (!od_info->freq_table)

		return freq_next;

drivers/cpufreq/cpufreq-dt.c

+105 −195
Original line number Diff line number Diff line
@@ -31,9 +31,8 @@ 


struct private_data {

	struct device *cpu_dev;

	struct regulator *cpu_reg;

	struct thermal_cooling_device *cdev;

	unsigned int voltage_tolerance; /* in percentage */

	const char *reg_name;

};



static struct freq_attr *cpufreq_dt_attr[] = {
@@ -44,175 +43,128 @@ static struct freq_attr *cpufreq_dt_attr[] = { 


static int set_target(struct cpufreq_policy *policy, unsigned int index)

{

	struct dev_pm_opp *opp;

	struct cpufreq_frequency_table *freq_table = policy->freq_table;

	struct clk *cpu_clk = policy->clk;

	struct private_data *priv = policy->driver_data;

	struct device *cpu_dev = priv->cpu_dev;

	struct regulator *cpu_reg = priv->cpu_reg;

	unsigned long volt = 0, tol = 0;

	int volt_old = 0;

	unsigned int old_freq, new_freq;

	long freq_Hz, freq_exact;

	int ret;



	freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);

	if (freq_Hz <= 0)

		freq_Hz = freq_table[index].frequency * 1000;



	freq_exact = freq_Hz;

	new_freq = freq_Hz / 1000;

	old_freq = clk_get_rate(cpu_clk) / 1000;

	return dev_pm_opp_set_rate(priv->cpu_dev,

				   policy->freq_table[index].frequency * 1000);

}



	if (!IS_ERR(cpu_reg)) {

		unsigned long opp_freq;

/*

 * An earlier version of opp-v1 bindings used to name the regulator

 * "cpu0-supply", we still need to handle that for backwards compatibility.

 */

static const char *find_supply_name(struct device *dev)

{

	struct device_node *np;

	struct property *pp;

	int cpu = dev->id;

	const char *name = NULL;



		rcu_read_lock();

		opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);

		if (IS_ERR(opp)) {

			rcu_read_unlock();

			dev_err(cpu_dev, "failed to find OPP for %ld\n",

				freq_Hz);

			return PTR_ERR(opp);

		}

		volt = dev_pm_opp_get_voltage(opp);

		opp_freq = dev_pm_opp_get_freq(opp);

		rcu_read_unlock();

		tol = volt * priv->voltage_tolerance / 100;

		volt_old = regulator_get_voltage(cpu_reg);

		dev_dbg(cpu_dev, "Found OPP: %ld kHz, %ld uV\n",

			opp_freq / 1000, volt);

	}

	np = of_node_get(dev->of_node);



	dev_dbg(cpu_dev, "%u MHz, %d mV --> %u MHz, %ld mV\n",

		old_freq / 1000, (volt_old > 0) ? volt_old / 1000 : -1,

		new_freq / 1000, volt ? volt / 1000 : -1);

	/* This must be valid for sure */

	if (WARN_ON(!np))

		return NULL;



	/* scaling up?  scale voltage before frequency */

	if (!IS_ERR(cpu_reg) && new_freq > old_freq) {

		ret = regulator_set_voltage_tol(cpu_reg, volt, tol);

		if (ret) {

			dev_err(cpu_dev, "failed to scale voltage up: %d\n",

				ret);

			return ret;

	/* Try "cpu0" for older DTs */

	if (!cpu) {

		pp = of_find_property(np, "cpu0-supply", NULL);

		if (pp) {

			name = "cpu0";

			goto node_put;

		}

	}



	ret = clk_set_rate(cpu_clk, freq_exact);

	if (ret) {

		dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);

		if (!IS_ERR(cpu_reg) && volt_old > 0)

			regulator_set_voltage_tol(cpu_reg, volt_old, tol);

		return ret;

	pp = of_find_property(np, "cpu-supply", NULL);

	if (pp) {

		name = "cpu";

		goto node_put;

	}



	/* scaling down?  scale voltage after frequency */

	if (!IS_ERR(cpu_reg) && new_freq < old_freq) {

		ret = regulator_set_voltage_tol(cpu_reg, volt, tol);

		if (ret) {

			dev_err(cpu_dev, "failed to scale voltage down: %d\n",

				ret);

			clk_set_rate(cpu_clk, old_freq * 1000);

		}

	}



	return ret;

	dev_dbg(dev, "no regulator for cpu%d\n", cpu);

node_put:

	of_node_put(np);

	return name;

}



static int allocate_resources(int cpu, struct device **cdev,

			      struct regulator **creg, struct clk **cclk)

static int resources_available(void)

{

	struct device *cpu_dev;

	struct regulator *cpu_reg;

	struct clk *cpu_clk;

	int ret = 0;

	char *reg_cpu0 = "cpu0", *reg_cpu = "cpu", *reg;

	const char *name;



	cpu_dev = get_cpu_device(cpu);

	cpu_dev = get_cpu_device(0);

	if (!cpu_dev) {

		pr_err("failed to get cpu%d device\n", cpu);

		pr_err("failed to get cpu0 device\n");

		return -ENODEV;

	}



	/* Try "cpu0" for older DTs */

	if (!cpu)

		reg = reg_cpu0;

	else

		reg = reg_cpu;



try_again:

	cpu_reg = regulator_get_optional(cpu_dev, reg);

	ret = PTR_ERR_OR_ZERO(cpu_reg);

	cpu_clk = clk_get(cpu_dev, NULL);

	ret = PTR_ERR_OR_ZERO(cpu_clk);

	if (ret) {

		/*

		 * If cpu's regulator supply node is present, but regulator is

		 * not yet registered, we should try defering probe.

		 * If cpu's clk node is present, but clock is not yet

		 * registered, we should try defering probe.

		 */

		if (ret == -EPROBE_DEFER) {

			dev_dbg(cpu_dev, "cpu%d regulator not ready, retry\n",

				cpu);

		if (ret == -EPROBE_DEFER)

			dev_dbg(cpu_dev, "clock not ready, retry\n");

		else

			dev_err(cpu_dev, "failed to get clock: %d\n", ret);



		return ret;

	}



		/* Try with "cpu-supply" */

		if (reg == reg_cpu0) {

			reg = reg_cpu;

			goto try_again;

		}

	clk_put(cpu_clk);



		dev_dbg(cpu_dev, "no regulator for cpu%d: %d\n", cpu, ret);

	}

	name = find_supply_name(cpu_dev);

	/* Platform doesn't require regulator */

	if (!name)

		return 0;



	cpu_clk = clk_get(cpu_dev, NULL);

	ret = PTR_ERR_OR_ZERO(cpu_clk);

	cpu_reg = regulator_get_optional(cpu_dev, name);

	ret = PTR_ERR_OR_ZERO(cpu_reg);

	if (ret) {

		/* put regulator */

		if (!IS_ERR(cpu_reg))

			regulator_put(cpu_reg);



		/*

		 * If cpu's clk node is present, but clock is not yet

		 * registered, we should try defering probe.

		 * If cpu's regulator supply node is present, but regulator is

		 * not yet registered, we should try defering probe.

		 */

		if (ret == -EPROBE_DEFER)

			dev_dbg(cpu_dev, "cpu%d clock not ready, retry\n", cpu);

			dev_dbg(cpu_dev, "cpu0 regulator not ready, retry\n");

		else

			dev_err(cpu_dev, "failed to get cpu%d clock: %d\n", cpu,

				ret);

	} else {

		*cdev = cpu_dev;

		*creg = cpu_reg;

		*cclk = cpu_clk;

	}

			dev_dbg(cpu_dev, "no regulator for cpu0: %d\n", ret);



		return ret;

	}



	regulator_put(cpu_reg);

	return 0;

}



static int cpufreq_init(struct cpufreq_policy *policy)

{

	struct cpufreq_frequency_table *freq_table;

	struct device_node *np;

	struct private_data *priv;

	struct device *cpu_dev;

	struct regulator *cpu_reg;

	struct clk *cpu_clk;

	struct dev_pm_opp *suspend_opp;

	unsigned long min_uV = ~0, max_uV = 0;

	unsigned int transition_latency;

	bool need_update = false;

	bool opp_v1 = false;

	const char *name;

	int ret;



	ret = allocate_resources(policy->cpu, &cpu_dev, &cpu_reg, &cpu_clk);

	if (ret) {

		pr_err("%s: Failed to allocate resources: %d\n", __func__, ret);

		return ret;

	cpu_dev = get_cpu_device(policy->cpu);

	if (!cpu_dev) {

		pr_err("failed to get cpu%d device\n", policy->cpu);

		return -ENODEV;

	}



	np = of_node_get(cpu_dev->of_node);

	if (!np) {

		dev_err(cpu_dev, "failed to find cpu%d node\n", policy->cpu);

		ret = -ENOENT;

		goto out_put_reg_clk;

	cpu_clk = clk_get(cpu_dev, NULL);

	if (IS_ERR(cpu_clk)) {

		ret = PTR_ERR(cpu_clk);

		dev_err(cpu_dev, "%s: failed to get clk: %d\n", __func__, ret);

		return ret;

	}



	/* Get OPP-sharing information from "operating-points-v2" bindings */
@@ -223,9 +175,23 @@ static int cpufreq_init(struct cpufreq_policy *policy) 
		 * finding shared-OPPs for backward compatibility.

		 */

		if (ret == -ENOENT)

			need_update = true;

			opp_v1 = true;

		else

			goto out_node_put;

			goto out_put_clk;

	}



	/*

	 * OPP layer will be taking care of regulators now, but it needs to know

	 * the name of the regulator first.

	 */

	name = find_supply_name(cpu_dev);

	if (name) {

		ret = dev_pm_opp_set_regulator(cpu_dev, name);

		if (ret) {

			dev_err(cpu_dev, "Failed to set regulator for cpu%d: %d\n",

				policy->cpu, ret);

			goto out_put_clk;

		}

	}



	/*
@@ -246,12 +212,12 @@ static int cpufreq_init(struct cpufreq_policy *policy) 
	 */

	ret = dev_pm_opp_get_opp_count(cpu_dev);

	if (ret <= 0) {

		pr_debug("OPP table is not ready, deferring probe\n");

		dev_dbg(cpu_dev, "OPP table is not ready, deferring probe\n");

		ret = -EPROBE_DEFER;

		goto out_free_opp;

	}



	if (need_update) {

	if (opp_v1) {

		struct cpufreq_dt_platform_data *pd = cpufreq_get_driver_data();



		if (!pd || !pd->independent_clocks)
@@ -265,10 +231,6 @@ static int cpufreq_init(struct cpufreq_policy *policy) 
		if (ret)

			dev_err(cpu_dev, "%s: failed to mark OPPs as shared: %d\n",

				__func__, ret);



		of_property_read_u32(np, "clock-latency", &transition_latency);

	} else {

		transition_latency = dev_pm_opp_get_max_clock_latency(cpu_dev);

	}



	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
@@ -277,62 +239,16 @@ static int cpufreq_init(struct cpufreq_policy *policy) 
		goto out_free_opp;

	}



	of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance);



	if (!transition_latency)

		transition_latency = CPUFREQ_ETERNAL;



	if (!IS_ERR(cpu_reg)) {

		unsigned long opp_freq = 0;



		/*

		 * Disable any OPPs where the connected regulator isn't able to

		 * provide the specified voltage and record minimum and maximum

		 * voltage levels.

		 */

		while (1) {

			struct dev_pm_opp *opp;

			unsigned long opp_uV, tol_uV;



			rcu_read_lock();

			opp = dev_pm_opp_find_freq_ceil(cpu_dev, &opp_freq);

			if (IS_ERR(opp)) {

				rcu_read_unlock();

				break;

			}

			opp_uV = dev_pm_opp_get_voltage(opp);

			rcu_read_unlock();



			tol_uV = opp_uV * priv->voltage_tolerance / 100;

			if (regulator_is_supported_voltage(cpu_reg,

							   opp_uV - tol_uV,

							   opp_uV + tol_uV)) {

				if (opp_uV < min_uV)

					min_uV = opp_uV;

				if (opp_uV > max_uV)

					max_uV = opp_uV;

			} else {

				dev_pm_opp_disable(cpu_dev, opp_freq);

			}



			opp_freq++;

		}



		ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);

		if (ret > 0)

			transition_latency += ret * 1000;

	}

	priv->reg_name = name;



	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);

	if (ret) {

		pr_err("failed to init cpufreq table: %d\n", ret);

		dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);

		goto out_free_priv;

	}



	priv->cpu_dev = cpu_dev;

	priv->cpu_reg = cpu_reg;

	policy->driver_data = priv;



	policy->clk = cpu_clk;



	rcu_read_lock();
@@ -357,9 +273,11 @@ static int cpufreq_init(struct cpufreq_policy *policy) 
		cpufreq_dt_attr[1] = &cpufreq_freq_attr_scaling_boost_freqs;

	}



	policy->cpuinfo.transition_latency = transition_latency;

	transition_latency = dev_pm_opp_get_max_transition_latency(cpu_dev);

	if (!transition_latency)

		transition_latency = CPUFREQ_ETERNAL;



	of_node_put(np);

	policy->cpuinfo.transition_latency = transition_latency;



	return 0;
@@ -369,12 +287,10 @@ out_free_priv: 
	kfree(priv);

out_free_opp:

	dev_pm_opp_of_cpumask_remove_table(policy->cpus);

out_node_put:

	of_node_put(np);

out_put_reg_clk:

	if (name)

		dev_pm_opp_put_regulator(cpu_dev);

out_put_clk:

	clk_put(cpu_clk);

	if (!IS_ERR(cpu_reg))

		regulator_put(cpu_reg);



	return ret;

}
@@ -386,9 +302,10 @@ static int cpufreq_exit(struct cpufreq_policy *policy) 
	cpufreq_cooling_unregister(priv->cdev);

	dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table);

	dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);

	if (priv->reg_name)

		dev_pm_opp_put_regulator(priv->cpu_dev);



	clk_put(policy->clk);

	if (!IS_ERR(priv->cpu_reg))

		regulator_put(priv->cpu_reg);

	kfree(priv);



	return 0;
@@ -441,9 +358,6 @@ static struct cpufreq_driver dt_cpufreq_driver = { 


static int dt_cpufreq_probe(struct platform_device *pdev)

{

	struct device *cpu_dev;

	struct regulator *cpu_reg;

	struct clk *cpu_clk;

	int ret;



	/*
@@ -453,19 +367,15 @@ static int dt_cpufreq_probe(struct platform_device *pdev) 
	 *

	 * FIXME: Is checking this only for CPU0 sufficient ?

	 */

	ret = allocate_resources(0, &cpu_dev, &cpu_reg, &cpu_clk);

	ret = resources_available();

	if (ret)

		return ret;



	clk_put(cpu_clk);

	if (!IS_ERR(cpu_reg))

		regulator_put(cpu_reg);



	dt_cpufreq_driver.driver_data = dev_get_platdata(&pdev->dev);



	ret = cpufreq_register_driver(&dt_cpufreq_driver);

	if (ret)

		dev_err(cpu_dev, "failed register driver: %d\n", ret);

		dev_err(&pdev->dev, "failed register driver: %d\n", ret);



	return ret;

}

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