Commit 4ebcfd9a authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'Add-MT7629-ethernet-support' 



Sean Wang says:

====================
Add MT7629 ethernet support

MT7629 inlcudes two sets of SGMIIs used for external switch or PHY, and embedded
switch (ESW) via GDM1, GePHY via GMAC2, so add several patches in the series to
make the code base common with the old SoCs.

The patch 1, 3 and 6, adds extension for SGMII to have the hardware configured
for 1G, 2.5G and AN to fit the capability of the target PHY. In patch 6 could be
an example showing how to use these configurations for underlying PHY speed to
match up the link speed of the target PHY.

The patch 4 is used for automatically configured the hardware path from GMACx to
the target PHY by the description in deviceetree topology to determine the
proper value for the corresponding MUX.

The patch 2 and 5 is for the update for MT7629 including dt-binding document and
its driver.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 2789c14d afdede61

Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt

+2 −0
Original line number Diff line number Diff line
@@ -9,6 +9,8 @@ Required Properties: 
	- "mediatek,mt7622-sgmiisys", "syscon"

	- "mediatek,mt7629-sgmiisys", "syscon"

- #clock-cells: Must be 1

- mediatek,physpeed: Should be one of "auto", "1000" or "2500" to match up

		     the capability of the target PHY.



The SGMIISYS controller uses the common clk binding from

Documentation/devicetree/bindings/clock/clock-bindings.txt

Documentation/devicetree/bindings/net/mediatek-net.txt

+12 −2
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ Required properties: 
		"mediatek,mt2701-eth": for MT2701 SoC

		"mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC

		"mediatek,mt7622-eth": for MT7622 SoC

		"mediatek,mt7629-eth": for MT7629 SoC

- reg: Address and length of the register set for the device

- interrupts: Should contain the three frame engines interrupts in numeric

	order. These are fe_int0, fe_int1 and fe_int2.
@@ -19,14 +20,23 @@ Required properties: 
	"ethif", "esw", "gp2", "gp1" : For MT2701 and MT7623 SoC

        "ethif", "esw", "gp0", "gp1", "gp2", "sgmii_tx250m", "sgmii_rx250m",

	"sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" : For MT7622 SoC

	"ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "sgmii_tx250m",

	"sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii2_tx250m",

	"sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", "sgmii_ck",

	"eth2pll" : For MT7629 SoC.

- power-domains: phandle to the power domain that the ethernet is part of

- resets: Should contain phandles to the ethsys reset signals

- reset-names: Should contain the names of reset signal listed in the resets

		property

		These are "fe", "gmac" and "ppe"

- mediatek,ethsys: phandle to the syscon node that handles the port setup

- mediatek,sgmiisys: phandle to the syscon node that handles the SGMII setup

	which is required for those SoCs equipped with SGMII such as MT7622 SoC.

- mediatek,infracfg: phandle to the syscon node that handles the path from

	GMAC to PHY variants, which is required for MT7629 SoC.

- mediatek,sgmiisys: a list of phandles to the syscon node that handles the

	SGMII setup which is required for those SoCs equipped with SGMII such

	as MT7622 and MT7629 SoC. And MT7622 have only one set of SGMII shared

	by GMAC1 and GMAC2; MT7629 have two independent sets of SGMII directed

	to GMAC1 and GMAC2, respectively.

- mediatek,pctl: phandle to the syscon node that handles the ports slew rate

	and driver current: only for MT2701 and MT7623 SoC

arch/arm64/boot/dts/mediatek/mt7622.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -929,7 +929,8 @@ 
	sgmiisys: sgmiisys@1b128000 {

		compatible = "mediatek,mt7622-sgmiisys",

			     "syscon";

		reg = <0 0x1b128000 0 0x1000>;

		reg = <0 0x1b128000 0 0x3000>;

		#clock-cells = <1>;

		mediatek,physpeed = "2500";

	};

};

drivers/net/ethernet/mediatek/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -3,4 +3,5 @@ 
# Makefile for the Mediatek SoCs built-in ethernet macs

#



obj-$(CONFIG_NET_MEDIATEK_SOC)			+= mtk_eth_soc.o
 
obj-$(CONFIG_NET_MEDIATEK_SOC)                 += mtk_eth_soc.o mtk_sgmii.o \

						  mtk_eth_path.o

drivers/net/ethernet/mediatek/mtk_eth_path.c

0 → 100644
+323 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

// Copyright (c) 2018-2019 MediaTek Inc.



/* A library for configuring path from GMAC/GDM to target PHY

 *

 * Author: Sean Wang <sean.wang@mediatek.com>

 *

 */



#include <linux/phy.h>

#include <linux/regmap.h>



#include "mtk_eth_soc.h"



struct mtk_eth_muxc {

	int (*set_path)(struct mtk_eth *eth, int path);

};



static const char * const mtk_eth_mux_name[] = {

	"mux_gdm1_to_gmac1_esw", "mux_gmac2_gmac0_to_gephy",

	"mux_u3_gmac2_to_qphy", "mux_gmac1_gmac2_to_sgmii_rgmii",

	"mux_gmac12_to_gephy_sgmii",

};



static const char * const mtk_eth_path_name[] = {

	"gmac1_rgmii", "gmac1_trgmii", "gmac1_sgmii", "gmac2_rgmii",

	"gmac2_sgmii", "gmac2_gephy", "gdm1_esw",

};



static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, int path)

{

	bool updated = true;

	u32 val, mask, set;



	switch (path) {

	case MTK_ETH_PATH_GMAC1_SGMII:

		mask = ~(u32)MTK_MUX_TO_ESW;

		set = 0;

		break;

	case MTK_ETH_PATH_GDM1_ESW:

		mask = ~(u32)MTK_MUX_TO_ESW;

		set = MTK_MUX_TO_ESW;

		break;

	default:

		updated = false;

		break;

	};



	if (updated) {

		val = mtk_r32(eth, MTK_MAC_MISC);

		val = (val & mask) | set;

		mtk_w32(eth, val, MTK_MAC_MISC);

	}



	dev_dbg(eth->dev, "path %s in %s updated = %d\n",

		mtk_eth_path_name[path], __func__, updated);



	return 0;

}



static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, int path)

{

	unsigned int val = 0;

	bool updated = true;



	switch (path) {

	case MTK_ETH_PATH_GMAC2_GEPHY:

		val = ~(u32)GEPHY_MAC_SEL;

		break;

	default:

		updated = false;

		break;

	}



	if (updated)

		regmap_update_bits(eth->infra, INFRA_MISC2, GEPHY_MAC_SEL, val);



	dev_dbg(eth->dev, "path %s in %s updated = %d\n",

		mtk_eth_path_name[path], __func__, updated);



	return 0;

}



static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, int path)

{

	unsigned int val = 0;

	bool updated = true;



	switch (path) {

	case MTK_ETH_PATH_GMAC2_SGMII:

		val = CO_QPHY_SEL;

		break;

	default:

		updated = false;

		break;

	}



	if (updated)

		regmap_update_bits(eth->infra, INFRA_MISC2, CO_QPHY_SEL, val);



	dev_dbg(eth->dev, "path %s in %s updated = %d\n",

		mtk_eth_path_name[path], __func__, updated);



	return 0;

}



static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, int path)

{

	unsigned int val = 0;

	bool updated = true;



	switch (path) {

	case MTK_ETH_PATH_GMAC1_SGMII:

		val = SYSCFG0_SGMII_GMAC1;

		break;

	case MTK_ETH_PATH_GMAC2_SGMII:

		val = SYSCFG0_SGMII_GMAC2;

		break;

	case MTK_ETH_PATH_GMAC1_RGMII:

	case MTK_ETH_PATH_GMAC2_RGMII:

		regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);

		val &= SYSCFG0_SGMII_MASK;



		if ((path == MTK_GMAC1_RGMII && val == SYSCFG0_SGMII_GMAC1) ||

		    (path == MTK_GMAC2_RGMII && val == SYSCFG0_SGMII_GMAC2))

			val = 0;

		else

			updated = false;

		break;

	default:

		updated = false;

		break;

	};



	if (updated)

		regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,

				   SYSCFG0_SGMII_MASK, val);



	dev_dbg(eth->dev, "path %s in %s updated = %d\n",

		mtk_eth_path_name[path], __func__, updated);



	return 0;

}



static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, int path)

{

	unsigned int val = 0;

	bool updated = true;



	regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);



	switch (path) {

	case MTK_ETH_PATH_GMAC1_SGMII:

		val |= SYSCFG0_SGMII_GMAC1_V2;

		break;

	case MTK_ETH_PATH_GMAC2_GEPHY:

		val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2;

		break;

	case MTK_ETH_PATH_GMAC2_SGMII:

		val |= SYSCFG0_SGMII_GMAC2_V2;

		break;

	default:

		updated = false;

	};



	if (updated)

		regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,

				   SYSCFG0_SGMII_MASK, val);



	dev_dbg(eth->dev, "path %s in %s updated = %d\n",

		mtk_eth_path_name[path], __func__, updated);



	return 0;

}



static const struct mtk_eth_muxc mtk_eth_muxc[] = {

	{ .set_path = set_mux_gdm1_to_gmac1_esw, },

	{ .set_path = set_mux_gmac2_gmac0_to_gephy, },

	{ .set_path = set_mux_u3_gmac2_to_qphy, },

	{ .set_path = set_mux_gmac1_gmac2_to_sgmii_rgmii, },

	{ .set_path = set_mux_gmac12_to_gephy_sgmii, }

};



static int mtk_eth_mux_setup(struct mtk_eth *eth, int path)

{

	int i, err = 0;



	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_PATH_BIT(path))) {

		dev_err(eth->dev, "path %s isn't support on the SoC\n",

			mtk_eth_path_name[path]);

		return -EINVAL;

	}



	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_MUX))

		return 0;



	/* Setup MUX in path fabric */

	for (i = 0; i < MTK_ETH_MUX_MAX; i++) {

		if (MTK_HAS_CAPS(eth->soc->caps, MTK_MUX_BIT(i))) {

			err = mtk_eth_muxc[i].set_path(eth, path);

			if (err)

				goto out;

		} else {

			dev_dbg(eth->dev, "mux %s isn't present on the SoC\n",

				mtk_eth_mux_name[i]);

		}

	}



out:

	return err;

}



static int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)

{

	unsigned int val = 0;

	int sid, err, path;



	path = (mac_id == 0) ?  MTK_ETH_PATH_GMAC1_SGMII :

				MTK_ETH_PATH_GMAC2_SGMII;



	/* Setup proper MUXes along the path */

	err = mtk_eth_mux_setup(eth, path);

	if (err)

		return err;



	/* The path GMAC to SGMII will be enabled once the SGMIISYS is being

	 * setup done.

	 */

	regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);



	regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,

			   SYSCFG0_SGMII_MASK, ~(u32)SYSCFG0_SGMII_MASK);



	/* Decide how GMAC and SGMIISYS be mapped */

	sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 0 : mac_id;



	/* Setup SGMIISYS with the determined property */

	if (MTK_HAS_FLAGS(eth->sgmii->flags[sid], MTK_SGMII_PHYSPEED_AN))

		err = mtk_sgmii_setup_mode_an(eth->sgmii, sid);

	else

		err = mtk_sgmii_setup_mode_force(eth->sgmii, sid);



	if (err)

		return err;



	regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,

			   SYSCFG0_SGMII_MASK, val);



	return 0;

}



static int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id)

{

	int err, path = 0;



	if (mac_id == 1)

		path = MTK_ETH_PATH_GMAC2_GEPHY;



	if (!path)

		return -EINVAL;



	/* Setup proper MUXes along the path */

	err = mtk_eth_mux_setup(eth, path);

	if (err)

		return err;



	return 0;

}



static int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id)

{

	int err, path;



	path = (mac_id == 0) ?  MTK_ETH_PATH_GMAC1_RGMII :

				MTK_ETH_PATH_GMAC2_RGMII;



	/* Setup proper MUXes along the path */

	err = mtk_eth_mux_setup(eth, path);

	if (err)

		return err;



	return 0;

}



int mtk_setup_hw_path(struct mtk_eth *eth, int mac_id, int phymode)

{

	int err;



	switch (phymode) {

	case PHY_INTERFACE_MODE_TRGMII:

	case PHY_INTERFACE_MODE_RGMII_TXID:

	case PHY_INTERFACE_MODE_RGMII_RXID:

	case PHY_INTERFACE_MODE_RGMII_ID:

	case PHY_INTERFACE_MODE_RGMII:

	case PHY_INTERFACE_MODE_MII:

	case PHY_INTERFACE_MODE_REVMII:

	case PHY_INTERFACE_MODE_RMII:

		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) {

			err = mtk_gmac_rgmii_path_setup(eth, mac_id);

			if (err)

				return err;

		}

		break;

	case PHY_INTERFACE_MODE_SGMII:

		if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {

			err = mtk_gmac_sgmii_path_setup(eth, mac_id);

			if (err)

				return err;

		}

		break;

	case PHY_INTERFACE_MODE_GMII:

		if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) {

			err = mtk_gmac_gephy_path_setup(eth, mac_id);

			if (err)

				return err;

		}

		break;

	default:

		break;

	}



	return 0;

}

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