Commit 4eab8a57 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-intel-fixes' of git://anongit.freedesktop.org/~ickle/drm-intel 

* 'drm-intel-fixes' of git://anongit.freedesktop.org/~ickle/drm-intel: (25 commits)
  intel_agp,i915: Add more sandybridge graphics device ids
  drm/i915: Enable MI_FLUSH on Sandybridge
  agp/intel: Fix cache control for Sandybridge
  agp/intel: use #ifdef idiom for intel-agp.h
  agp/intel: fix physical address mask bits for sandybridge
  drm/i915: Prevent double dpms on
  drm/i915: Avoid use of uninitialised values when disabling panel-fitter
  drm/i915: Avoid pageflipping freeze when we miss the flip prepare interrupt
  drm/i915: Tightly scope intel_encoder to prevent invalid use
  drm/i915: Allocate the PCI resource for the MCHBAR
  drm/i915/dp: Really try 5 times before giving up.
  drm/i915/sdvo: Restore guess of the DDC bus in absence of VBIOS
  drm/i915/dp: Boost timeout for enabling transcoder to 100ms
  drm/i915: Re-use set_base_atomic to share setting of the display registers
  drm/i915: Fix offset page-flips on i965+
  drm/i915: Include a generation number in the device info
  i915: return -EFAULT if copy_to_user fails
  i915: return -EFAULT if copy_to_user fails
  agp/intel: Promote warning about failure to setup flush to error.
  drm/i915: overlay on gen2 can't address above 1G
  ...
parents 6300d6d7 85540480

drivers/char/agp/intel-agp.c

+13 −3
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <asm/smp.h>

#include "agp.h"

#include "intel-agp.h"

#include <linux/intel-gtt.h>



#include "intel-gtt.c"
@@ -815,11 +816,19 @@ static const struct intel_driver_description { 
	    "HD Graphics", NULL, &intel_i965_driver },

	{ PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,

	    "HD Graphics", NULL, &intel_i965_driver },

	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG,

	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,

	    "Sandybridge", NULL, &intel_gen6_driver },

	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG,

	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,

	    "Sandybridge", NULL, &intel_gen6_driver },

	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_D0_IG,

	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,

	    "Sandybridge", NULL, &intel_gen6_driver },

	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,

	    "Sandybridge", NULL, &intel_gen6_driver },

	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,

	    "Sandybridge", NULL, &intel_gen6_driver },

	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,

	    "Sandybridge", NULL, &intel_gen6_driver },

	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,

	    "Sandybridge", NULL, &intel_gen6_driver },

	{ 0, 0, NULL, NULL, NULL }

};
@@ -1044,6 +1053,7 @@ static struct pci_device_id agp_intel_pci_table[] = { 
	ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),

	ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB),

	ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB),

	ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB),

	{ }

};

drivers/char/agp/intel-agp.h

+16 −6
Original line number Diff line number Diff line 
/*

 * Common Intel AGPGART and GTT definitions.

 */

#ifndef _INTEL_AGP_H

#define _INTEL_AGP_H



/* Intel registers */

#define INTEL_APSIZE	0xb4
@@ -200,11 +202,16 @@ 
#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB	    0x0062

#define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB    0x006a

#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG	    0x0046

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB  0x0100

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG  0x0102

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB  0x0104

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG  0x0106

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_D0_IG  0x0126

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB		0x0100  /* Desktop */

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG		0x0102

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG		0x0112

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG	0x0122

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB		0x0104  /* Mobile */

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG	0x0106

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG	0x0116

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG	0x0126

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB		0x0108  /* Server */

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG		0x010A



/* cover 915 and 945 variants */

#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
@@ -231,7 +238,8 @@ 
		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)



#define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB)



#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
@@ -244,3 +252,5 @@ 
		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \

		IS_SNB)



#endif

drivers/char/agp/intel-gtt.c

+48 −18
Original line number Diff line number Diff line
@@ -49,6 +49,26 @@ static struct gatt_mask intel_i810_masks[] = 
	 .type = INTEL_AGP_CACHED_MEMORY}

};



#define INTEL_AGP_UNCACHED_MEMORY              0

#define INTEL_AGP_CACHED_MEMORY_LLC            1

#define INTEL_AGP_CACHED_MEMORY_LLC_GFDT       2

#define INTEL_AGP_CACHED_MEMORY_LLC_MLC        3

#define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT   4



static struct gatt_mask intel_gen6_masks[] =

{

	{.mask = I810_PTE_VALID | GEN6_PTE_UNCACHED,

	 .type = INTEL_AGP_UNCACHED_MEMORY },

	{.mask = I810_PTE_VALID | GEN6_PTE_LLC,

         .type = INTEL_AGP_CACHED_MEMORY_LLC },

	{.mask = I810_PTE_VALID | GEN6_PTE_LLC | GEN6_PTE_GFDT,

         .type = INTEL_AGP_CACHED_MEMORY_LLC_GFDT },

	{.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC,

         .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC },

	{.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC | GEN6_PTE_GFDT,

         .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT },

};



static struct _intel_private {

	struct pci_dev *pcidev;	/* device one */

	u8 __iomem *registers;
@@ -178,13 +198,6 @@ static void intel_agp_insert_sg_entries(struct agp_memory *mem, 
					off_t pg_start, int mask_type)

{

	int i, j;

	u32 cache_bits = 0;



	if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||

	    agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)

	{

		cache_bits = GEN6_PTE_LLC_MLC;

	}



	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {

		writel(agp_bridge->driver->mask_memory(agp_bridge,
@@ -317,6 +330,23 @@ static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, 
		return 0;

}



static int intel_gen6_type_to_mask_type(struct agp_bridge_data *bridge,

					int type)

{

	unsigned int type_mask = type & ~AGP_USER_CACHED_MEMORY_GFDT;

	unsigned int gfdt = type & AGP_USER_CACHED_MEMORY_GFDT;



	if (type_mask == AGP_USER_UNCACHED_MEMORY)

		return INTEL_AGP_UNCACHED_MEMORY;

	else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC)

		return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT :

			      INTEL_AGP_CACHED_MEMORY_LLC_MLC;

	else /* set 'normal'/'cached' to LLC by default */

		return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_GFDT :

			      INTEL_AGP_CACHED_MEMORY_LLC;

}





static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,

				int type)

{
@@ -588,8 +618,7 @@ static void intel_i830_init_gtt_entries(void) 
			gtt_entries = 0;

			break;

		}

	} else if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||

		   agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) {

	} else if (IS_SNB) {

		/*

		 * SandyBridge has new memory control reg at 0x50.w

		 */
@@ -1068,11 +1097,11 @@ static void intel_i9xx_setup_flush(void) 
		intel_i915_setup_chipset_flush();

	}



	if (intel_private.ifp_resource.start) {

	if (intel_private.ifp_resource.start)

		intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);

	if (!intel_private.i9xx_flush_page)

			dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");

	}

		dev_err(&intel_private.pcidev->dev,

			"can't ioremap flush page - no chipset flushing\n");

}



static int intel_i9xx_configure(void)
@@ -1163,7 +1192,7 @@ static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, 


	mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);



	if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&

	if (!IS_SNB && mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&

	    mask_type != INTEL_AGP_CACHED_MEMORY)

		goto out_err;
@@ -1333,8 +1362,8 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, 
static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge,

					    dma_addr_t addr, int type)

{

	/* Shift high bits down */

	addr |= (addr >> 28) & 0xff;

	/* gen6 has bit11-4 for physical addr bit39-32 */

	addr |= (addr >> 28) & 0xff0;



	/* Type checking must be done elsewhere */

	return addr | bridge->driver->masks[type].mask;
@@ -1359,6 +1388,7 @@ static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) 
		break;

	case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB:

	case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB:

	case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB:

		*gtt_offset = MB(2);



		pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
@@ -1563,7 +1593,7 @@ static const struct agp_bridge_driver intel_gen6_driver = { 
	.fetch_size		= intel_i9xx_fetch_size,

	.cleanup		= intel_i915_cleanup,

	.mask_memory		= intel_gen6_mask_memory,

	.masks			= intel_i810_masks,

	.masks			= intel_gen6_masks,

	.agp_enable		= intel_i810_agp_enable,

	.cache_flush		= global_cache_flush,

	.create_gatt_table	= intel_i965_create_gatt_table,
@@ -1576,7 +1606,7 @@ static const struct agp_bridge_driver intel_gen6_driver = { 
	.agp_alloc_pages        = agp_generic_alloc_pages,

	.agp_destroy_page	= agp_generic_destroy_page,

	.agp_destroy_pages      = agp_generic_destroy_pages,

	.agp_type_to_mask_type	= intel_i830_type_to_mask_type,

	.agp_type_to_mask_type	= intel_gen6_type_to_mask_type,

	.chipset_flush		= intel_i915_chipset_flush,

#ifdef USE_PCI_DMA_API

	.agp_map_page		= intel_agp_map_page,

drivers/gpu/drm/i915/i915_debugfs.c

+50 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
#include <linux/slab.h>

#include "drmP.h"

#include "drm.h"

#include "intel_drv.h"

#include "i915_drm.h"

#include "i915_drv.h"
@@ -121,6 +122,54 @@ static int i915_gem_object_list_info(struct seq_file *m, void *data) 
	return 0;

}



static int i915_gem_pageflip_info(struct seq_file *m, void *data)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	unsigned long flags;

	struct intel_crtc *crtc;



	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {

		const char *pipe = crtc->pipe ? "B" : "A";

		const char *plane = crtc->plane ? "B" : "A";

		struct intel_unpin_work *work;



		spin_lock_irqsave(&dev->event_lock, flags);

		work = crtc->unpin_work;

		if (work == NULL) {

			seq_printf(m, "No flip due on pipe %s (plane %s)\n",

				   pipe, plane);

		} else {

			if (!work->pending) {

				seq_printf(m, "Flip queued on pipe %s (plane %s)\n",

					   pipe, plane);

			} else {

				seq_printf(m, "Flip pending (waiting for vsync) on pipe %s (plane %s)\n",

					   pipe, plane);

			}

			if (work->enable_stall_check)

				seq_printf(m, "Stall check enabled, ");

			else

				seq_printf(m, "Stall check waiting for page flip ioctl, ");

			seq_printf(m, "%d prepares\n", work->pending);



			if (work->old_fb_obj) {

				struct drm_i915_gem_object *obj_priv = to_intel_bo(work->old_fb_obj);

				if(obj_priv)

					seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj_priv->gtt_offset );

			}

			if (work->pending_flip_obj) {

				struct drm_i915_gem_object *obj_priv = to_intel_bo(work->pending_flip_obj);

				if(obj_priv)

					seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj_priv->gtt_offset );

			}

		}

		spin_unlock_irqrestore(&dev->event_lock, flags);

	}



	return 0;

}



static int i915_gem_request_info(struct seq_file *m, void *data)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -777,6 +826,7 @@ static struct drm_info_list i915_debugfs_list[] = { 
	{"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},

	{"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},

	{"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},

	{"i915_gem_pageflip", i915_gem_pageflip_info, 0},

	{"i915_gem_request", i915_gem_request_info, 0},

	{"i915_gem_seqno", i915_gem_seqno_info, 0},

	{"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},

drivers/gpu/drm/i915/i915_dma.c

+23 −13
Original line number Diff line number Diff line
@@ -620,9 +620,11 @@ static int i915_batchbuffer(struct drm_device *dev, void *data, 
		ret = copy_from_user(cliprects, batch->cliprects,

				     batch->num_cliprects *

				     sizeof(struct drm_clip_rect));

		if (ret != 0)

		if (ret != 0) {

			ret = -EFAULT;

			goto fail_free;

		}

	}



	mutex_lock(&dev->struct_mutex);

	ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
@@ -662,8 +664,10 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data, 
		return -ENOMEM;



	ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);

	if (ret != 0)

	if (ret != 0) {

		ret = -EFAULT;

		goto fail_batch_free;

	}



	if (cmdbuf->num_cliprects) {

		cliprects = kcalloc(cmdbuf->num_cliprects,
@@ -676,9 +680,11 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data, 
		ret = copy_from_user(cliprects, cmdbuf->cliprects,

				     cmdbuf->num_cliprects *

				     sizeof(struct drm_clip_rect));

		if (ret != 0)

		if (ret != 0) {

			ret = -EFAULT;

			goto fail_clip_free;

		}

	}



	mutex_lock(&dev->struct_mutex);

	ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
@@ -885,7 +891,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev) 
	int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;

	u32 temp_lo, temp_hi = 0;

	u64 mchbar_addr;

	int ret = 0;

	int ret;



	if (IS_I965G(dev))

		pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
@@ -895,14 +901,15 @@ intel_alloc_mchbar_resource(struct drm_device *dev) 
	/* If ACPI doesn't have it, assume we need to allocate it ourselves */

#ifdef CONFIG_PNP

	if (mchbar_addr &&

	    pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {

		ret = 0;

		goto out;

	}

	    pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))

		return 0;

#endif



	/* Get some space for it */

	ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,

	dev_priv->mch_res.name = "i915 MCHBAR";

	dev_priv->mch_res.flags = IORESOURCE_MEM;

	ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,

				     &dev_priv->mch_res,

				     MCHBAR_SIZE, MCHBAR_SIZE,

				     PCIBIOS_MIN_MEM,

				     0, pcibios_align_resource,
@@ -910,7 +917,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev) 
	if (ret) {

		DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);

		dev_priv->mch_res.start = 0;

		goto out;

		return ret;

	}



	if (IS_I965G(dev))
@@ -919,8 +926,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev) 


	pci_write_config_dword(dev_priv->bridge_dev, reg,

			       lower_32_bits(dev_priv->mch_res.start));

out:

	return ret;

	return 0;

}



/* Setup MCHBAR if possible, return true if we should disable it again */
@@ -2082,6 +2088,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
		goto free_priv;

	}



	/* overlay on gen2 is broken and can't address above 1G */

	if (IS_GEN2(dev))

		dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));



	dev_priv->regs = ioremap(base, size);

	if (!dev_priv->regs) {

		DRM_ERROR("failed to map registers\n");

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