Commit 4e80c8f5 authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Linus Walleij
Browse files

pinctrl: intel: Add Intel Merrifield pin controller support 



This driver adds pinctrl support for Intel Merrifield. The IP block which is
called Family-Level Interface Shim is a separate entity in SoC. The GPIO driver
(gpio-intel-mid.c) will be updated accordingly to support pinctrl interface.

Reviewed-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 11884b18

drivers/pinctrl/intel/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -29,6 +29,17 @@ config PINCTRL_CHERRYVIEW 
	  Cherryview/Braswell pinctrl driver provides an interface that

	  allows configuring of SoC pins and using them as GPIOs.



config PINCTRL_MERRIFIELD

	tristate "Intel Merrifield pinctrl driver"

	depends on X86_INTEL_MID

	select PINMUX

	select PINCONF

	select GENERIC_PINCONF

	help

	  Merrifield Family-Level Interface Shim (FLIS) driver provides an

	  interface that allows configuring of SoC pins and using them as

	  GPIOs.



config PINCTRL_INTEL

	tristate

	select PINMUX

drivers/pinctrl/intel/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 


obj-$(CONFIG_PINCTRL_BAYTRAIL)		+= pinctrl-baytrail.o

obj-$(CONFIG_PINCTRL_CHERRYVIEW)	+= pinctrl-cherryview.o

obj-$(CONFIG_PINCTRL_MERRIFIELD)	+= pinctrl-merrifield.o

obj-$(CONFIG_PINCTRL_INTEL)		+= pinctrl-intel.o

obj-$(CONFIG_PINCTRL_BROXTON)		+= pinctrl-broxton.o

obj-$(CONFIG_PINCTRL_SUNRISEPOINT)	+= pinctrl-sunrisepoint.o

drivers/pinctrl/intel/pinctrl-merrifield.c

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File added.

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