Commit 4e79f021 authored Sep 21, 2020 by Ard Biesheuvel

ARM: p2v: fix handling of LPAE translation in BE mode

When running in BE mode on LPAE hardware with a PA-to-VA translation
that exceeds 4 GB, we patch bits 39:32 of the offset into the wrong
byte of the opcode. So fix that, by rotating the offset in r0 to the
right by 8 bits, which will put the 8-bit immediate in bits 31:24.

Note that this will also move bit #22 in its correct place when
applying the rotation to the constant #0x400000.

Fixes: d9a790df ("ARM: 7883/1: fix mov to mvn conversion in case of 64 bit phys_addr_t and BE")
Acked-by: Nicolas Pitre <nico@fluxnic.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>

parent 3650b228

arch/arm/kernel/head.S

+1 −5

Original line number	Diff line number	Diff line
		@@ -671,12 +671,8 @@ ARM_BE8(rev16 ip, ip)
		ldrcc r7, [r4], #4 @ use branch for delay slot
		bcc 1b
		bx lr
		#else
		#ifdef CONFIG_CPU_ENDIAN_BE8
		moveq r0, #0x00004000 @ set bit 22, mov to mvn instruction
		#else
		moveq r0, #0x400000 @ set bit 22, mov to mvn instruction
		#endif
		b 2f
		1: ldr ip, [r7, r3]
		#ifdef CONFIG_CPU_ENDIAN_BE8
		@@ -685,7 +681,7 @@ ARM_BE8(rev16 ip, ip)
		tst ip, #0x000f0000 @ check the rotation field
		orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24
		biceq ip, ip, #0x00004000 @ clear bit 22
		orreq ip, ip, r0 @ mask in offset bits 7-0
		orreq ip, ip, r0, ror #8 @ mask in offset bits 7-0
		#else
		bic ip, ip, #0x000000ff
		tst ip, #0xf00 @ check the rotation field

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