Commit 4e71e085 authored by Kevin Wang's avatar Kevin Wang Committed by Alex Deucher
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drm/amdgpu/swSMU: custom UMD pstate peak clock for navi14 



add navi14 umd pstate peak clock support.

NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK   1670 MHz
NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK  1448 MHz
NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK  1181 MHz
NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK  1717 MHz
NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK   1448 MHz

Signed-off-by: default avatarKevin Wang <kevin1.wang@amd.com>
Reviewed-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7e899409

drivers/gpu/drm/amd/powerplay/navi10_ppt.c

+39 −14
Original line number Diff line number Diff line
@@ -1467,6 +1467,8 @@ static int navi10_set_peak_clock_by_device(struct smu_context *smu) 
	uint32_t sclk_freq = 0, uclk_freq = 0;

	uint32_t uclk_level = 0;



	switch (adev->asic_type) {

	case CHIP_NAVI10:

		switch (adev->pdev->revision) {

		case 0xf0: /* XTX */

		case 0xc0:
@@ -1480,6 +1482,33 @@ static int navi10_set_peak_clock_by_device(struct smu_context *smu) 
			sclk_freq = NAVI10_PEAK_SCLK_XL;

			break;

		}

		break;

	case CHIP_NAVI14:

		switch (adev->pdev->revision) {

		case 0xc7: /* XT */

		case 0xf4:

			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;

			break;

		case 0xc1: /* XTM */

		case 0xf2:

			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;

			break;

		case 0xc3: /* XLM */

		case 0xf3:

			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;

			break;

		case 0xc5: /* XTX */

		case 0xf6:

			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;

			break;

		default: /* XL */

			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;

			break;

		}

		break;

	default:

		return -EINVAL;

	}



	ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_level);

	if (ret)
@@ -1501,10 +1530,6 @@ static int navi10_set_peak_clock_by_device(struct smu_context *smu) 
static int navi10_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)

{

	int ret = 0;

	struct amdgpu_device *adev = smu->adev;



	if (adev->asic_type != CHIP_NAVI10)

		return -EINVAL;



	switch (level) {

	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:

drivers/gpu/drm/amd/powerplay/navi10_ppt.h

+6 −0
Original line number Diff line number Diff line
@@ -27,6 +27,12 @@ 
#define NAVI10_PEAK_SCLK_XT  		(1755)

#define NAVI10_PEAK_SCLK_XL  		(1625)



#define NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK      (1670)

#define NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK     (1448)

#define NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK     (1181)

#define NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK     (1717)

#define NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK      (1448)



extern void navi10_set_ppt_funcs(struct smu_context *smu);



#endif

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