Commit 4e638ae9 authored by Xiangliang Yu's avatar Xiangliang Yu Committed by Alex Deucher
Browse files

drm/amdgpu/gfx8: add support kernel interface queue(KIQ) 



KIQ is queue-memory based initialization method: setup KIQ queue
firstly, then send command to KIQ to setup other queues, without
accessing registers.

For virtualization, need KIQ to access virtual function registers
when running on guest mode.

V2: use amdgpu_bo_create/free_kernel to allocate BO.

Signed-off-by: default avatarMonk Liu <Monk.Liu@amd.com>
Signed-off-by: default avatarXiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarChunming Zhou <david1.zhou@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b64a18c5

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+13 −0
Original line number Diff line number Diff line
@@ -183,6 +183,11 @@ enum amdgpu_thermal_irq { 
	AMDGPU_THERMAL_IRQ_LAST

};



enum amdgpu_kiq_irq {

	AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,

	AMDGPU_CP_KIQ_IRQ_LAST

};



int amdgpu_set_clockgating_state(struct amdgpu_device *adev,

				  enum amd_ip_block_type block_type,

				  enum amd_clockgating_state state);
@@ -775,6 +780,13 @@ struct amdgpu_mec { 
	u32 num_queue;

};



struct amdgpu_kiq {

	u64			eop_gpu_addr;

	struct amdgpu_bo	*eop_obj;

	struct amdgpu_ring	ring;

	struct amdgpu_irq_src	irq;

};



/*

 * GPU scratch registers structures, functions & helpers

 */
@@ -850,6 +862,7 @@ struct amdgpu_gfx { 
	struct amdgpu_gca_config	config;

	struct amdgpu_rlc		rlc;

	struct amdgpu_mec		mec;

	struct amdgpu_kiq		kiq;

	struct amdgpu_scratch		scratch;

	const struct firmware		*me_fw;	/* ME firmware */

	uint32_t			me_fw_version;

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+605 −2

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/amdgpu/vid.h

+2 −0
Original line number Diff line number Diff line
@@ -360,6 +360,8 @@ 
#define	PACKET3_WAIT_ON_CE_COUNTER			0x86

#define	PACKET3_WAIT_ON_DE_COUNTER_DIFF			0x88

#define	PACKET3_SWITCH_BUFFER				0x8B

#define	PACKET3_SET_RESOURCES				0xA0

#define	PACKET3_MAP_QUEUES				0xA2



#define VCE_CMD_NO_OP		0x00000000

#define VCE_CMD_END		0x00000001

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