Commit 4e53a92c authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'clk/aspeed' into aspeed/dts 



The clk/aspeed branch gets merged through the clk
maintainers, pulling it in as a prerequisite for
the aspeed G6 DT files.

* clk/aspeed:
  clk: Add support for AST2600 SoC
  clk: aspeed: Move structures to header
  clk: aspeed: Add SDIO gate

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 5f9e832c d3d04f6c

drivers/clk/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o 
obj-$(CONFIG_COMMON_CLK_FIXED_MMIO)	+= clk-fixed-mmio.o

obj-$(CONFIG_COMMON_CLK_GEMINI)		+= clk-gemini.o

obj-$(CONFIG_COMMON_CLK_ASPEED)		+= clk-aspeed.o

obj-$(CONFIG_MACH_ASPEED_G6)		+= clk-ast2600.o

obj-$(CONFIG_ARCH_HIGHBANK)		+= clk-highbank.o

obj-$(CONFIG_CLK_HSDK)			+= clk-hsdk-pll.o

obj-$(CONFIG_COMMON_CLK_LOCHNAGAR)	+= clk-lochnagar.o

drivers/clk/clk-aspeed.c

+11 −67
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0+

// Copyright IBM Corp



#define pr_fmt(fmt) "clk-aspeed: " fmt



#include <linux/clk-provider.h>

#include <linux/mfd/syscon.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include <linux/platform_device.h>

#include <linux/regmap.h>

#include <linux/reset-controller.h>

#include <linux/slab.h>

#include <linux/spinlock.h>



#include <dt-bindings/clock/aspeed-clock.h>



#include "clk-aspeed.h"



#define ASPEED_NUM_CLKS		36



#define ASPEED_RESET2_OFFSET	32
@@ -42,48 +42,6 @@ static struct clk_hw_onecell_data *aspeed_clk_data; 


static void __iomem *scu_base;



/**

 * struct aspeed_gate_data - Aspeed gated clocks

 * @clock_idx: bit used to gate this clock in the clock register

 * @reset_idx: bit used to reset this IP in the reset register. -1 if no

 *             reset is required when enabling the clock

 * @name: the clock name

 * @parent_name: the name of the parent clock

 * @flags: standard clock framework flags

 */

struct aspeed_gate_data {

	u8		clock_idx;

	s8		reset_idx;

	const char	*name;

	const char	*parent_name;

	unsigned long	flags;

};



/**

 * struct aspeed_clk_gate - Aspeed specific clk_gate structure

 * @hw:		handle between common and hardware-specific interfaces

 * @reg:	register controlling gate

 * @clock_idx:	bit used to gate this clock in the clock register

 * @reset_idx:	bit used to reset this IP in the reset register. -1 if no

 *		reset is required when enabling the clock

 * @flags:	hardware-specific flags

 * @lock:	register lock

 *

 * Some of the clocks in the Aspeed SoC must be put in reset before enabling.

 * This modified version of clk_gate allows an optional reset bit to be

 * specified.

 */

struct aspeed_clk_gate {

	struct clk_hw	hw;

	struct regmap	*map;

	u8		clock_idx;

	s8		reset_idx;

	u8		flags;

	spinlock_t	*lock;

};



#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)



/* TODO: ask Aspeed about the actual parent data */

static const struct aspeed_gate_data aspeed_gates[] = {

	/*				 clk rst   name			parent	flags */
@@ -208,13 +166,6 @@ static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val) 
			mult, div);

}



struct aspeed_clk_soc_data {

	const struct clk_div_table *div_table;

	const struct clk_div_table *eclk_div_table;

	const struct clk_div_table *mac_div_table;

	struct clk_hw *(*calc_pll)(const char *name, u32 val);

};



static const struct aspeed_clk_soc_data ast2500_data = {

	.div_table = ast2500_div_table,

	.eclk_div_table = ast2500_eclk_div_table,
@@ -315,18 +266,6 @@ static const struct clk_ops aspeed_clk_gate_ops = { 
	.is_enabled = aspeed_clk_is_enabled,

};



/**

 * struct aspeed_reset - Aspeed reset controller

 * @map: regmap to access the containing system controller

 * @rcdev: reset controller device

 */

struct aspeed_reset {

	struct regmap			*map;

	struct reset_controller_dev	rcdev;

};



#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)



static const u8 aspeed_resets[] = {

	/* SCU04 resets */

	[ASPEED_RESET_XDMA]	= 25,
@@ -500,9 +439,14 @@ static int aspeed_clk_probe(struct platform_device *pdev) 
		return PTR_ERR(hw);

	aspeed_clk_data->hws[ASPEED_CLK_MPLL] =	hw;



	/* SD/SDIO clock divider (TODO: There's a gate too) */

	hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0,

			scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,

	/* SD/SDIO clock divider and gate */

	hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,

				  scu_base + ASPEED_CLK_SELECTION, 15, 0,

				  &aspeed_clk_lock);

	if (IS_ERR(hw))

		return PTR_ERR(hw);

	hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",

			0, scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,

			soc_data->div_table,

			&aspeed_clk_lock);

	if (IS_ERR(hw))

drivers/clk/clk-aspeed.h

0 → 100644
+82 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-or-later */

/*

 * Structures used by ASPEED clock drivers

 *

 * Copyright 2019 IBM Corp.

 */



#include <linux/clk-provider.h>

#include <linux/kernel.h>

#include <linux/reset-controller.h>

#include <linux/spinlock.h>



struct clk_div_table;

struct regmap;



/**

 * struct aspeed_gate_data - Aspeed gated clocks

 * @clock_idx: bit used to gate this clock in the clock register

 * @reset_idx: bit used to reset this IP in the reset register. -1 if no

 *             reset is required when enabling the clock

 * @name: the clock name

 * @parent_name: the name of the parent clock

 * @flags: standard clock framework flags

 */

struct aspeed_gate_data {

	u8		clock_idx;

	s8		reset_idx;

	const char	*name;

	const char	*parent_name;

	unsigned long	flags;

};



/**

 * struct aspeed_clk_gate - Aspeed specific clk_gate structure

 * @hw:		handle between common and hardware-specific interfaces

 * @reg:	register controlling gate

 * @clock_idx:	bit used to gate this clock in the clock register

 * @reset_idx:	bit used to reset this IP in the reset register. -1 if no

 *		reset is required when enabling the clock

 * @flags:	hardware-specific flags

 * @lock:	register lock

 *

 * Some of the clocks in the Aspeed SoC must be put in reset before enabling.

 * This modified version of clk_gate allows an optional reset bit to be

 * specified.

 */

struct aspeed_clk_gate {

	struct clk_hw	hw;

	struct regmap	*map;

	u8		clock_idx;

	s8		reset_idx;

	u8		flags;

	spinlock_t	*lock;

};



#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)



/**

 * struct aspeed_reset - Aspeed reset controller

 * @map: regmap to access the containing system controller

 * @rcdev: reset controller device

 */

struct aspeed_reset {

	struct regmap			*map;

	struct reset_controller_dev	rcdev;

};



#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)



/**

 * struct aspeed_clk_soc_data - Aspeed SoC specific divisor information

 * @div_table: Common divider lookup table

 * @eclk_div_table: Divider lookup table for ECLK

 * @mac_div_table: Divider lookup table for MAC (Ethernet) clocks

 * @calc_pll: Callback to maculate common PLL settings

 */

struct aspeed_clk_soc_data {

	const struct clk_div_table *div_table;

	const struct clk_div_table *eclk_div_table;

	const struct clk_div_table *mac_div_table;

	struct clk_hw *(*calc_pll)(const char *name, u32 val);

};

drivers/clk/clk-ast2600.c

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+704 −0

File added.

Preview size limit exceeded, changes collapsed.

include/dt-bindings/clock/ast2600-clock.h

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+113 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */

#ifndef DT_BINDINGS_AST2600_CLOCK_H

#define DT_BINDINGS_AST2600_CLOCK_H



#define ASPEED_CLK_GATE_ECLK		0

#define ASPEED_CLK_GATE_GCLK		1



#define ASPEED_CLK_GATE_MCLK		2



#define ASPEED_CLK_GATE_VCLK		3

#define ASPEED_CLK_GATE_BCLK		4

#define ASPEED_CLK_GATE_DCLK		5



#define ASPEED_CLK_GATE_LCLK		6

#define ASPEED_CLK_GATE_LHCCLK		7



#define ASPEED_CLK_GATE_D1CLK		8

#define ASPEED_CLK_GATE_YCLK		9



#define ASPEED_CLK_GATE_REF0CLK		10

#define ASPEED_CLK_GATE_REF1CLK		11



#define ASPEED_CLK_GATE_ESPICLK		12



#define ASPEED_CLK_GATE_USBUHCICLK	13

#define ASPEED_CLK_GATE_USBPORT1CLK	14

#define ASPEED_CLK_GATE_USBPORT2CLK	15



#define ASPEED_CLK_GATE_RSACLK		16

#define ASPEED_CLK_GATE_RVASCLK		17



#define ASPEED_CLK_GATE_MAC1CLK		18

#define ASPEED_CLK_GATE_MAC2CLK		19

#define ASPEED_CLK_GATE_MAC3CLK		20

#define ASPEED_CLK_GATE_MAC4CLK		21



#define ASPEED_CLK_GATE_UART1CLK	22

#define ASPEED_CLK_GATE_UART2CLK	23

#define ASPEED_CLK_GATE_UART3CLK	24

#define ASPEED_CLK_GATE_UART4CLK	25

#define ASPEED_CLK_GATE_UART5CLK	26

#define ASPEED_CLK_GATE_UART6CLK	27

#define ASPEED_CLK_GATE_UART7CLK	28

#define ASPEED_CLK_GATE_UART8CLK	29

#define ASPEED_CLK_GATE_UART9CLK	30

#define ASPEED_CLK_GATE_UART10CLK	31

#define ASPEED_CLK_GATE_UART11CLK	32

#define ASPEED_CLK_GATE_UART12CLK	33

#define ASPEED_CLK_GATE_UART13CLK	34



#define ASPEED_CLK_GATE_SDCLK		35

#define ASPEED_CLK_GATE_EMMCCLK		36



#define ASPEED_CLK_GATE_I3C0CLK		37

#define ASPEED_CLK_GATE_I3C1CLK		38

#define ASPEED_CLK_GATE_I3C2CLK		39

#define ASPEED_CLK_GATE_I3C3CLK		40

#define ASPEED_CLK_GATE_I3C4CLK		41

#define ASPEED_CLK_GATE_I3C5CLK		42

#define ASPEED_CLK_GATE_I3C6CLK		43

#define ASPEED_CLK_GATE_I3C7CLK		44



#define ASPEED_CLK_GATE_FSICLK		45



#define ASPEED_CLK_HPLL			46

#define ASPEED_CLK_MPLL			47

#define ASPEED_CLK_DPLL			48

#define ASPEED_CLK_EPLL			49

#define ASPEED_CLK_APLL			50

#define ASPEED_CLK_AHB			51

#define ASPEED_CLK_APB1			52

#define ASPEED_CLK_APB2			53

#define ASPEED_CLK_BCLK			54

#define ASPEED_CLK_D1CLK		55

#define ASPEED_CLK_VCLK			56

#define ASPEED_CLK_LHCLK		57

#define ASPEED_CLK_UART			58

#define ASPEED_CLK_UARTX		59

#define ASPEED_CLK_SDIO			60

#define ASPEED_CLK_EMMC			61

#define ASPEED_CLK_ECLK			62

#define ASPEED_CLK_ECLK_MUX		63

#define ASPEED_CLK_MAC12		64

#define ASPEED_CLK_MAC34		65

#define ASPEED_CLK_USBPHY_40M		66



/* Only list resets here that are not part of a gate */

#define ASPEED_RESET_ADC		55

#define ASPEED_RESET_JTAG_MASTER2	54

#define ASPEED_RESET_I3C_DMA		39

#define ASPEED_RESET_PWM		37

#define ASPEED_RESET_PECI		36

#define ASPEED_RESET_MII		35

#define ASPEED_RESET_I2C		34

#define ASPEED_RESET_H2X		31

#define ASPEED_RESET_GP_MCU		30

#define ASPEED_RESET_DP_MCU		29

#define ASPEED_RESET_DP			28

#define ASPEED_RESET_RC_XDMA		27

#define ASPEED_RESET_GRAPHICS		26

#define ASPEED_RESET_DEV_XDMA		25

#define ASPEED_RESET_DEV_MCTP		24

#define ASPEED_RESET_RC_MCTP		23

#define ASPEED_RESET_JTAG_MASTER	22

#define ASPEED_RESET_PCIE_DEV_O		21

#define ASPEED_RESET_PCIE_DEV_OEN	20

#define ASPEED_RESET_PCIE_RC_O		19

#define ASPEED_RESET_PCIE_RC_OEN	18

#define ASPEED_RESET_PCI_DP		5

#define ASPEED_RESET_AHB		1

#define ASPEED_RESET_SDRAM		0



#endif

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