Commit 4e3f77d8 authored by Jan Beulich's avatar Jan Beulich Committed by Juergen Gross
Browse files

xen/mcelog: add PPIN to record when available 



This is to augment commit 3f5a7896 ("x86/mce: Include the PPIN in MCE
records when available").

I'm also adding "synd" and "ipid" fields to struct xen_mce, in an
attempt to keep field offsets in sync with struct mce. These two fields
won't get populated for now, though.

Signed-off-by: default avatarJan Beulich <jbeulich@suse.com>
Reviewed-by: default avatarBoris Ostrovsky <boris.ostrovsky@oracle.com>
Signed-off-by: default avatarJuergen Gross <jgross@suse.com>
parent ca8ffdae

arch/x86/include/asm/msr-index.h

+2 −0
Original line number Diff line number Diff line
@@ -393,6 +393,8 @@ 
#define MSR_AMD_PSTATE_DEF_BASE		0xc0010064

#define MSR_AMD64_OSVW_ID_LENGTH	0xc0010140

#define MSR_AMD64_OSVW_STATUS		0xc0010141

#define MSR_AMD_PPIN_CTL		0xc00102f0

#define MSR_AMD_PPIN			0xc00102f1

#define MSR_AMD64_LS_CFG		0xc0011020

#define MSR_AMD64_DC_CFG		0xc0011022

#define MSR_AMD64_BU_CFG2		0xc001102a

drivers/xen/mcelog.c

+5 −0
Original line number Diff line number Diff line
@@ -253,6 +253,11 @@ static int convert_log(struct mc_info *mi) 
		case MSR_IA32_MCG_CAP:

			m.mcgcap = g_physinfo[i].mc_msrvalues[j].value;

			break;



		case MSR_PPIN:

		case MSR_AMD_PPIN:

			m.ppin = g_physinfo[i].mc_msrvalues[j].value;

			break;

		}



	mic = NULL;

include/xen/interface/xen-mca.h

+8 −1
Original line number Diff line number Diff line
@@ -331,7 +331,11 @@ struct xen_mc { 
};

DEFINE_GUEST_HANDLE_STRUCT(xen_mc);



/* Fields are zero when not available */

/*

 * Fields are zero when not available. Also, this struct is shared with

 * userspace mcelog and thus must keep existing fields at current offsets.

 * Only add new fields to the end of the structure

 */

struct xen_mce {

	__u64 status;

	__u64 misc;
@@ -352,6 +356,9 @@ struct xen_mce { 
	__u32 socketid;	/* CPU socket ID */

	__u32 apicid;	/* CPU initial apic ID */

	__u64 mcgcap;	/* MCGCAP MSR: machine check capabilities of CPU */

	__u64 synd;	/* MCA_SYND MSR: only valid on SMCA systems */

	__u64 ipid;	/* MCA_IPID MSR: only valid on SMCA systems */

	__u64 ppin;	/* Protected Processor Inventory Number */

};



/*

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