Commit 4dea04c1 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into clk-next 

Pull Amlogic clk driver updates from Jerome Brunet:

 * Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH)
 * Add new compatible to the meson8 clock controller for meson8b
 * Add missing parents to gxbb clk81

* tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson:
  clk: meson: gxbb: add all clk81 parents
  clk: meson: meson8b: add compatibles for Meson8 and Meson8m2
  clk: meson8b: export the ethernet gate clock
  clk: meson8b: export the USB clocks
  clk: meson8b: export the gate clock for the HW random number generator
  clk: meson8b: export the SDIO clock
  clk: meson8b: export the SAR ADC clocks
parents ef748cb3 215c80a7

Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt

+7 −4
Original line number Diff line number Diff line 
* Amlogic Meson8b Clock and Reset Unit

* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit



The Amlogic Meson8b clock controller generates and supplies clock to various

controllers within the SoC.

The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and

supplies clock to various controllers within the SoC.



Required Properties:



- compatible: should be "amlogic,meson8b-clkc"

- compatible: must be one of:

	- "amlogic,meson8-clkc" for Meson8 (S802) SoCs

	- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs

	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs

- reg: it must be composed by two tuples:

	0) physical base address of the xtal register and length of memory

	   mapped region.

drivers/clk/meson/Kconfig

+3 −3
Original line number Diff line number Diff line
@@ -7,9 +7,9 @@ config COMMON_CLK_MESON8B 
	bool

	depends on COMMON_CLK_AMLOGIC

	help

	  Support for the clock controller on AmLogic S805 devices, aka

	  meson8b. Say Y if you want peripherals and CPU frequency scaling to

	  work.

	  Support for the clock controller on AmLogic S802 (Meson8),

	  S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you

	  want peripherals and CPU frequency scaling to work.



config COMMON_CLK_GXBB

	bool

drivers/clk/meson/gxbb.c

+8 −5
Original line number Diff line number Diff line
@@ -603,7 +603,11 @@ static struct meson_clk_mpll gxbb_mpll2 = { 
 * coordinated clock rates feature

 */



static u32 mux_table_clk81[]	= { 6, 5, 7 };

static u32 mux_table_clk81[]	= { 0, 2, 3, 4, 5, 6, 7 };

static const char * const clk81_parent_names[] = {

	"xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",

	"fclk_div3", "fclk_div5"

};



static struct clk_mux gxbb_mpeg_clk_sel = {

	.reg = (void *)HHI_MPEG_CLK_CNTL,
@@ -616,13 +620,12 @@ static struct clk_mux gxbb_mpeg_clk_sel = { 
		.name = "mpeg_clk_sel",

		.ops = &clk_mux_ro_ops,

		/*

		 * FIXME bits 14:12 selects from 8 possible parents:

		 * bits 14:12 selects from 8 possible parents:

		 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,

		 * fclk_div4, fclk_div3, fclk_div5

		 */

		.parent_names = (const char *[]){ "fclk_div3", "fclk_div4",

			"fclk_div5" },

		.num_parents = 3,

		.parent_names = clk81_parent_names,

		.num_parents = ARRAY_SIZE(clk81_parent_names),

		.flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),

	},

};

drivers/clk/meson/meson8b.c

+4 −1
Original line number Diff line number Diff line 
/*

 * AmLogic S805 / Meson8b Clock Controller Driver

 * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller

 * Driver

 *

 * Copyright (c) 2015 Endless Mobile, Inc.

 * Author: Carlo Caione <carlo@endlessm.com>
@@ -777,7 +778,9 @@ iounmap: 
}



static const struct of_device_id meson8b_clkc_match_table[] = {

	{ .compatible = "amlogic,meson8-clkc" },

	{ .compatible = "amlogic,meson8b-clkc" },

	{ .compatible = "amlogic,meson8m2-clkc" },

	{ }

};

drivers/clk/meson/meson8b.h

+10 −10
Original line number Diff line number Diff line
@@ -87,20 +87,20 @@ 
#define CLKID_PERIPHS		20

#define CLKID_SPICC		21

#define CLKID_I2C		22

#define CLKID_SAR_ADC		23

/* #define CLKID_SAR_ADC */

#define CLKID_SMART_CARD	24

#define CLKID_RNG0		25

/* #define CLKID_RNG0 */

#define CLKID_UART0		26

#define CLKID_SDHC		27

#define CLKID_STREAM		28

#define CLKID_ASYNC_FIFO	29

#define CLKID_SDIO		30

/* #define CLKID_SDIO */

#define CLKID_ABUF		31

#define CLKID_HIU_IFACE		32

#define CLKID_ASSIST_MISC	33

#define CLKID_SPI		34

#define CLKID_I2S_SPDIF		35

#define CLKID_ETH		36

/* #define CLKID_ETH */

#define CLKID_DEMUX		37

#define CLKID_AIU_GLUE		38

#define CLKID_IEC958		39
@@ -114,12 +114,12 @@ 
#define CLKID_AIU		47

#define CLKID_UART1		48

#define CLKID_G2D		49

#define CLKID_USB0		50

#define CLKID_USB1		51

/* #define CLKID_USB0 */

/* #define CLKID_USB1 */

#define CLKID_RESET		52

#define CLKID_NAND		53

#define CLKID_DOS_PARSER	54

#define CLKID_USB		55

/* #define CLKID_USB */

#define CLKID_VDIN1		56

#define CLKID_AHB_ARB0		57

#define CLKID_EFUSE		58
@@ -128,12 +128,12 @@ 
#define CLKID_AHB_CTRL_BUS	61

#define CLKID_HDMI_INTR_SYNC	62

#define CLKID_HDMI_PCLK		63

#define CLKID_USB1_DDR_BRIDGE	64

#define CLKID_USB0_DDR_BRIDGE	65

/* CLKID_USB1_DDR_BRIDGE */

/* CLKID_USB0_DDR_BRIDGE */

#define CLKID_MMC_PCLK		66

#define CLKID_DVIN		67

#define CLKID_UART2		68

#define CLKID_SANA		69

/* #define CLKID_SANA */

#define CLKID_VPU_INTR		70

#define CLKID_SEC_AHB_AHB3_BRIDGE	71

#define CLKID_CLK81_A9		72

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