Commit 4de094ee authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Alex Deucher
Browse files

drm/amd/display: add REFCYC_PER_TRIP_TO_MEMORY programming 



it allows us to do urgent latency programming

Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: default avatarRoman Li <Roman.Li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 91c665bd

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+16 −0
Original line number Diff line number Diff line
@@ -2575,6 +2575,10 @@ void dcn20_calculate_wm( 
	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

#if defined(CONFIG_DRM_AMD_DC_DCN2_1)

	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

#endif



	if (vlevel < 2) {

		pipes[0].clks_cfg.voltage = 2;
@@ -2586,6 +2590,10 @@ void dcn20_calculate_wm( 
	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

#if defined(CONFIG_DRM_AMD_DC_DCN2_1)

	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

#endif



	if (vlevel < 3) {

		pipes[0].clks_cfg.voltage = 3;
@@ -2597,6 +2605,10 @@ void dcn20_calculate_wm( 
	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

#if defined(CONFIG_DRM_AMD_DC_DCN2_1)

	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

#endif



	pipes[0].clks_cfg.voltage = vlevel;

	pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
@@ -2606,6 +2618,10 @@ void dcn20_calculate_wm( 
	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

#if defined(CONFIG_DRM_AMD_DC_DCN2_1)

	context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

#endif

}



void dcn20_calculate_dlg_params(

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c

+35 −4
Original line number Diff line number Diff line
@@ -97,7 +97,7 @@ void dcn21_dchvm_init(struct hubbub *hubbub) 
	REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);

}



static int hubbub21_init_dchub(struct hubbub *hubbub,

int hubbub21_init_dchub(struct hubbub *hubbub,

		struct dcn_hubbub_phys_addr_config *pa_config)

{

	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
@@ -120,7 +120,7 @@ static int hubbub21_init_dchub(struct hubbub *hubbub, 
	return NUM_VMID;

}



static void hubbub21_program_urgent_watermarks(

void hubbub21_program_urgent_watermarks(

		struct hubbub *hubbub,

		struct dcn_watermark_set *watermarks,

		unsigned int refclk_mhz,
@@ -160,6 +160,13 @@ static void hubbub21_program_urgent_watermarks( 
		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0,

				DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, watermarks->a.frac_urg_bw_nom);

	}

	if (safe_to_lower || watermarks->a.urgent_latency_ns > hubbub1->watermarks.a.urgent_latency_ns) {

		hubbub1->watermarks.a.urgent_latency_ns = watermarks->a.urgent_latency_ns;

		prog_wm_value = convert_and_clamp(watermarks->a.urgent_latency_ns,

				refclk_mhz, 0x1fffff);

		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0,

				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, prog_wm_value);

	}



	/* clock state B */

	if (safe_to_lower || watermarks->b.urgent_ns > hubbub1->watermarks.b.urgent_ns) {
@@ -192,6 +199,14 @@ static void hubbub21_program_urgent_watermarks( 
				DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, watermarks->a.frac_urg_bw_nom);

	}



	if (safe_to_lower || watermarks->b.urgent_latency_ns > hubbub1->watermarks.b.urgent_latency_ns) {

		hubbub1->watermarks.b.urgent_latency_ns = watermarks->b.urgent_latency_ns;

		prog_wm_value = convert_and_clamp(watermarks->b.urgent_latency_ns,

				refclk_mhz, 0x1fffff);

		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0,

				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, prog_wm_value);

	}



	/* clock state C */

	if (safe_to_lower || watermarks->c.urgent_ns > hubbub1->watermarks.c.urgent_ns) {

		hubbub1->watermarks.c.urgent_ns = watermarks->c.urgent_ns;
@@ -223,6 +238,14 @@ static void hubbub21_program_urgent_watermarks( 
				DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, watermarks->a.frac_urg_bw_nom);

	}



	if (safe_to_lower || watermarks->c.urgent_latency_ns > hubbub1->watermarks.c.urgent_latency_ns) {

		hubbub1->watermarks.c.urgent_latency_ns = watermarks->c.urgent_latency_ns;

		prog_wm_value = convert_and_clamp(watermarks->c.urgent_latency_ns,

				refclk_mhz, 0x1fffff);

		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, 0,

				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, prog_wm_value);

	}



	/* clock state D */

	if (safe_to_lower || watermarks->d.urgent_ns > hubbub1->watermarks.d.urgent_ns) {

		hubbub1->watermarks.d.urgent_ns = watermarks->d.urgent_ns;
@@ -253,9 +276,17 @@ static void hubbub21_program_urgent_watermarks( 
		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0,

				DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, watermarks->a.frac_urg_bw_nom);

	}



	if (safe_to_lower || watermarks->d.urgent_latency_ns > hubbub1->watermarks.d.urgent_latency_ns) {

		hubbub1->watermarks.d.urgent_latency_ns = watermarks->d.urgent_latency_ns;

		prog_wm_value = convert_and_clamp(watermarks->d.urgent_latency_ns,

				refclk_mhz, 0x1fffff);

		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, 0,

				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, prog_wm_value);

	}

}



static void hubbub21_program_stutter_watermarks(

void hubbub21_program_stutter_watermarks(

		struct hubbub *hubbub,

		struct dcn_watermark_set *watermarks,

		unsigned int refclk_mhz,
@@ -389,7 +420,7 @@ static void hubbub21_program_stutter_watermarks( 
	}

}



static void hubbub21_program_pstate_watermarks(

void hubbub21_program_pstate_watermarks(

		struct hubbub *hubbub,

		struct dcn_watermark_set *watermarks,

		unsigned int refclk_mhz,

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h

+17 −0
Original line number Diff line number Diff line
@@ -114,11 +114,28 @@ 
	HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh)



void dcn21_dchvm_init(struct hubbub *hubbub);

int hubbub21_init_dchub(struct hubbub *hubbub,

		struct dcn_hubbub_phys_addr_config *pa_config);

void hubbub21_program_watermarks(

		struct hubbub *hubbub,

		struct dcn_watermark_set *watermarks,

		unsigned int refclk_mhz,

		bool safe_to_lower);

void hubbub21_program_urgent_watermarks(

		struct hubbub *hubbub,

		struct dcn_watermark_set *watermarks,

		unsigned int refclk_mhz,

		bool safe_to_lower);

void hubbub21_program_stutter_watermarks(

		struct hubbub *hubbub,

		struct dcn_watermark_set *watermarks,

		unsigned int refclk_mhz,

		bool safe_to_lower);

void hubbub21_program_pstate_watermarks(

		struct hubbub *hubbub,

		struct dcn_watermark_set *watermarks,

		unsigned int refclk_mhz,

		bool safe_to_lower);



void hubbub21_wm_read_state(struct hubbub *hubbub,

		struct dcn_hubbub_wm *wm);

drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h

+1 −0
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ struct dcn_watermarks { 
#if defined(CONFIG_DRM_AMD_DC_DCN2_1)

	uint32_t frac_urg_bw_nom;

	uint32_t frac_urg_bw_flip;

	int32_t urgent_latency_ns;

#endif

	struct cstate_pstate_watermarks_st cstate_pstate;

};

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