Commit 4dd1f579 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branches 'pci/host-exynos', 'pci/host-iproc', 'pci/host-keystone',... 

Merge branches 'pci/host-exynos', 'pci/host-iproc', 'pci/host-keystone', 'pci/host-layerscape', 'pci/host-mvebu', 'pci/host-rcar' and 'pci/host-versatile' into next

* pci/host-exynos:
  PCI: exynos: Fix INTx enablement statement termination error

* pci/host-iproc:
  PCI: iproc: Add Broadcom iProc PCIe support
  PCI: iproc: Add DT docs for Broadcom iProc PCIe driver
  PCI: Export symbols required for loadable host driver modules

* pci/host-keystone:
  PCI: keystone: Don't dereference possible NULL pointer

* pci/host-layerscape:
  PCI: layerscape: Simplify platform_get_resource_byname() failure checking

* pci/host-mvebu:
  PCI: mvebu: Add suspend/resume support

* pci/host-rcar:
  PCI: rcar: Verify that mem_res is 64K-aligned
  PCI: rcar: Change PCIEPARL and PCIEPARH to PCIEPALR and PCIEPAUR
  PCI: rcar: Write zeroes to reserved PCIEPARL bits
  PCI: rcar: Fix position of MSI enable bit

* pci/host-versatile:
  PCI: versatile: Check for devm_ioremap_resource() failures
parents 8e795840 01d06a9a 1fb37a81 f76ea574 e3dc17a5 ab14d45e 7a27db23 87358169

Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt

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* Broadcom iProc PCIe controller with the platform bus interface



Required properties:

- compatible: Must be "brcm,iproc-pcie"

- reg: base address and length of the PCIe controller I/O register space

- #interrupt-cells: set to <1>

- interrupt-map-mask and interrupt-map, standard PCI properties to define the

  mapping of the PCIe interface to interrupt numbers

- linux,pci-domain: PCI domain ID. Should be unique for each host controller

- bus-range: PCI bus numbers covered

- #address-cells: set to <3>

- #size-cells: set to <2>

- device_type: set to "pci"

- ranges: ranges for the PCI memory and I/O regions



Optional properties:

- phys: phandle of the PCIe PHY device

- phy-names: must be "pcie-phy"



Example:

	pcie0: pcie@18012000 {

		compatible = "brcm,iproc-pcie";

		reg = <0x18012000 0x1000>;



		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;



		linux,pci-domain = <0>;



		bus-range = <0x00 0xff>;



		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		ranges = <0x81000000 0 0	  0x28000000 0 0x00010000

			  0x82000000 0 0x20000000 0x20000000 0 0x04000000>;



		phys = <&phy 0 5>;

		phy-names = "pcie-phy";

	};



	pcie1: pcie@18013000 {

		compatible = "brcm,iproc-pcie";

		reg = <0x18013000 0x1000>;



		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;



		linux,pci-domain = <1>;



		bus-range = <0x00 0xff>;



		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		ranges = <0x81000000 0 0	  0x48000000 0 0x00010000

			  0x82000000 0 0x40000000 0x40000000 0 0x04000000>;



		phys = <&phy 1 6>;

		phy-names = "pcie-phy";

	};

drivers/pci/host/Kconfig

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@@ -106,4 +106,23 @@ config PCI_VERSATILE 
	bool "ARM Versatile PB PCI controller"

	depends on ARCH_VERSATILE



config PCIE_IPROC

	tristate "Broadcom iProc PCIe controller"

	depends on OF && ARM

	default n

	help

	  This enables the iProc PCIe core controller support for Broadcom's

	  iProc family of SoCs. An appropriate bus interface driver also needs

	  to be enabled



config PCIE_IPROC_PLATFORM

	tristate "Broadcom iProc PCIe platform bus driver"

	depends on ARCH_BCM_IPROC || (ARM && COMPILE_TEST)

	depends on OF

	select PCIE_IPROC

	default ARCH_BCM_IPROC

	help

	  Say Y here if you want to use the Broadcom iProc PCIe controller

	  through the generic platform bus interface



endmenu

drivers/pci/host/Makefile

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@@ -13,3 +13,5 @@ obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o 
obj-$(CONFIG_PCI_XGENE) += pci-xgene.o

obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o

obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o

obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o

obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o

drivers/pci/host/pci-exynos.c

+1 −1
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@@ -396,7 +396,7 @@ static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp) 


	/* enable INTX interrupt */

	val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |

		IRQ_INTC_ASSERT | IRQ_INTD_ASSERT,

		IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;

	exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE);

}

drivers/pci/host/pci-keystone-dw.c

+2 −1
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@@ -496,11 +496,12 @@ int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie, 


	/* Index 1 is the application reg. space address */

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);

	ks_pcie->app = *res;

	ks_pcie->va_app_base = devm_ioremap_resource(pp->dev, res);

	if (IS_ERR(ks_pcie->va_app_base))

		return PTR_ERR(ks_pcie->va_app_base);



	ks_pcie->app = *res;



	/* Create legacy IRQ domain */

	ks_pcie->legacy_irq_domain =

			irq_domain_add_linear(ks_pcie->legacy_intc_np,

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