Commit 4dc0a7ca authored by Michal Wajdeczko's avatar Michal Wajdeczko Committed by Chris Wilson
Browse files

drm/i915: Don't try to place HWS in non-existing mappable region 



HWS placement restrictions can't just rely on HAS_LLC flag.

Signed-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: default avatarMatthew Auld <matthew.auld@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191029095856.25431-5-matthew.auld@intel.com
parent 895d8ebe

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+1 −1
Original line number Diff line number Diff line
@@ -528,7 +528,7 @@ static int pin_ggtt_status_page(struct intel_engine_cs *engine, 
	unsigned int flags;



	flags = PIN_GLOBAL;

	if (!HAS_LLC(engine->i915))

	if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt))

		/*

		 * On g33, we cannot place HWS above 256MiB, so

		 * restrict its pinning to the low mappable arena.

CRA Git | Maintained and supported by SUSTech CRA and CCSE