Commit 4dbf09fe authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mtd/for-5.2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mtd/linux 

Pull MTD updates from Richard Weinberger:
 "MTD core changes:
   - New AFS partition parser
   - Update MAINTAINERS entry
   - Use of fall-throughs markers

  NAND core changes:
   - Support having the bad block markers in either the first, second or
     last page of a block. The combination of all three location is now
     possible.
   - Constification of NAND_OP_PARSER(_PATTERN) elements.
   - Generic NAND DT bindings changed to yaml format (can be used to
     check the proposed bindings. First platform to be fully supported:
     sunxi.
   - Stopped using several legacy hooks.
   - Preparation to use the generic NAND layer with the addition of
     several helpers and the removal of the struct nand_chip from
     generic functions.
   - Kconfig cleanup to prepare the introduction of external ECC engines
     support.
   - Fallthrough comments.
   - Introduction of the SPI-mem dirmap API for SPI-NAND devices.

  Raw NAND controller drivers changes:
   - nandsim:
      - Switch to ->exec-op().
   - meson:
      - Misc cleanups and fixes.
      - New OOB layout.
   - Sunxi:
      - A23/A33 NAND DMA support.
   - Ingenic:
      - Full reorganization and cleanup.
      - Clear separation between NAND controller and ECC engine.
      - Support JZ4740 an JZ4725B.
   - Denali:
      - Clear controller/chip separation.
      - ->exec_op() migration.
      - Various cleanups.
   - fsl_elbc:
      - Enable software ECC support.
   - Atmel:
      - Sam9x60 support.
   - GPMI:
      - Introduce the GPMI_IS_MXS() macro.
   - Various trivial/spelling/coding style fixes.

  SPI NOR core changes:
   - Print all JEDEC ID bytes on error
   - Fix comment of spi_nor_find_best_erase_type()
   - Add region locking flags for s25fl512s

  SPI NOR controller drivers changes:
   - intel-spi:
      - Avoid crossing 4K address boundary on read/write
      - Add support for Intel Comet Lake SPI serial flash"

* tag 'mtd/for-5.2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (120 commits)
  mtd: part: fix incorrect format specifier for an unsigned long long
  mtd: lpddr_cmds: Mark expected switch fall-through
  mtd: phram: Mark expected switch fall-throughs
  mtd: cfi_cmdset_0002: Mark expected switch fall-throughs
  mtd: cfi_util: mark expected switch fall-throughs
  MAINTAINERS: MTD Git repository is hosted on kernel.org
  MAINTAINERS: Update jffs2 entry
  mtd: afs: add v2 partition parsing
  mtd: afs: factor the IIS read into partition parser
  mtd: afs: factor footer parsing into the v1 part parsing
  mtd: factor out v1 partition parsing
  mtd: afs: simplify partition detection
  mtd: afs: simplify partition parsing
  mtd: partitions: Add OF support to AFS partitions
  mtd: partitions: Add AFS partitions DT bindings
  mtd: afs: Move AFS partition parser to parsers subdir
  mtd: maps: Make uclinux_ram_map static
  mtd: maps: Allow MTD_PHYSMAP with MTD_RAM
  MAINTAINERS: Add myself as MTD maintainer
  MAINTAINERS: Remove my name from the MTD and NAND entries
  ...
parents 983dfa4b 3008ba87

Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ Required properties: 
			"atmel,at91sam9g45-ebi"

			"atmel,at91sam9x5-ebi"

			"atmel,sama5d3-ebi"

			"microchip,sam9x60-ebi"



- reg:			Contains offset/length value for EBI memory mapping.

			This property might contain several entries if the EBI

Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml

0 → 100644
+97 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Allwinner A10 NAND Controller Device Tree Bindings



allOf:

  - $ref: "nand-controller.yaml"



maintainers:

  - Chen-Yu Tsai <wens@csie.org>

  - Maxime Ripard <maxime.ripard@bootlin.com>



properties:

  "#address-cells": true

  "#size-cells": true



  compatible:

    enum:

      - allwinner,sun4i-a10-nand

      - allwinner,sun8i-a23-nand-controller

  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    items:

      - description: Bus Clock

      - description: Module Clock



  clock-names:

    items:

      - const: ahb

      - const: mod



  resets:

    maxItems: 1



  reset-names:

    const: ahb



  dmas:

    maxItems: 1



  dma-names:

    const: rxtx



  pinctrl-names: true



patternProperties:

  "^pinctrl-[0-9]+$": true



  "^nand@[a-f0-9]+$":

    properties:

      reg:

        maxItems: 1

        minimum: 0

        maximum: 7



      nand-ecc-mode: true



      nand-ecc-algo:

        const: bch



      nand-ecc-step-size:

        enum: [ 512, 1024 ]



      nand-ecc-strength:

        maximum: 80



      allwinner,rb:

        description:

          Contains the native Ready/Busy IDs.

        allOf:

          - $ref: /schemas/types.yaml#/definitions/uint32-array

          - minItems: 1

            maxItems: 2

            items:

              minimum: 0

              maximum: 1



    additionalProperties: false



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names



additionalProperties: false



...

Documentation/devicetree/bindings/mtd/atmel-nand.txt

+1 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ Required properties: 
	"atmel,at91sam9261-nand-controller"

	"atmel,at91sam9g45-nand-controller"

	"atmel,sama5d3-nand-controller"

	"microchip,sam9x60-nand-controller"

- ranges: empty ranges property to forward EBI ranges definitions.

- #address-cells: should be set to 2.

- #size-cells: should be set to 1.

Documentation/devicetree/bindings/mtd/denali-nand.txt

+27 −13
Original line number Diff line number Diff line
@@ -7,13 +7,23 @@ Required properties: 
      "socionext,uniphier-denali-nand-v5b"  - for Socionext UniPhier (v5b)

  - reg : should contain registers location and length for data and reg.

  - reg-names: Should contain the reg names "nand_data" and "denali_reg"

  - #address-cells: should be 1. The cell encodes the chip select connection.

  - #size-cells : should be 0.

  - interrupts : The interrupt number.

  - clocks: should contain phandle of the controller core clock, the bus

    interface clock, and the ECC circuit clock.

  - clock-names: should contain "nand", "nand_x", "ecc"



Sub-nodes:

  Sub-nodes represent available NAND chips.



  Required properties:

    - reg: should contain the bank ID of the controller to which each chip

      select is connected.



  Optional properties:

  - nand-ecc-step-size: see nand.txt for details.  If present, the value must be

    - nand-ecc-step-size: see nand.txt for details.

      If present, the value must be

        512        for "altr,socfpga-denali-nand"

        1024       for "socionext,uniphier-denali-nand-v5a"

        1024       for "socionext,uniphier-denali-nand-v5b"
@@ -23,18 +33,22 @@ Optional properties: 
        8, 16      for "socionext,uniphier-denali-nand-v5b"

    - nand-ecc-maximize: see nand.txt for details



The device tree may optionally contain sub-nodes describing partitions of the

The chip nodes may optionally contain sub-nodes describing partitions of the

address space. See partition.txt for more detail.



Examples:



nand: nand@ff900000 {

	#address-cells = <1>;

	#size-cells = <1>;

	#size-cells = <0>;

	compatible = "altr,socfpga-denali-nand";

	reg = <0xff900000 0x20>, <0xffb80000 0x1000>;

	reg-names = "nand_data", "denali_reg";

	clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;

	clock-names = "nand", "nand_x", "ecc";

	interrupts = <0 144 4>;



	nand@0 {

		reg = <0>;

	}

};

Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt

+19 −13
Original line number Diff line number Diff line 
* Ingenic JZ4780 NAND/BCH

* Ingenic JZ4780 NAND/ECC



This file documents the device tree bindings for NAND flash devices on the

JZ4780. NAND devices are connected to the NEMC controller (described in
@@ -6,15 +6,18 @@ memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must 
be children of the NEMC node.



Required NAND controller device properties:

- compatible: Should be set to "ingenic,jz4780-nand".

- compatible: Should be one of:

  * ingenic,jz4740-nand

  * ingenic,jz4725b-nand

  * ingenic,jz4780-nand

- reg: For each bank with a NAND chip attached, should specify a bank number,

  an offset of 0 and a size of 0x1000000 (i.e. the whole NEMC bank).



Optional NAND controller device properties:

- ingenic,bch-controller: To make use of the hardware BCH controller, this

  property must contain a phandle for the BCH controller node. The required

- ecc-engine: To make use of the hardware ECC controller, this

  property must contain a phandle for the ECC controller node. The required

  properties for this node are described below. If this is not specified,

  software BCH will be used instead.

  software ECC will be used instead.



Optional children nodes:

- Individual NAND chips are children of the NAND controller node.
@@ -45,7 +48,7 @@ nemc: nemc@13410000 { 
		#address-cells = <1>;

		#size-cells = <0>;



		ingenic,bch-controller = <&bch>;

		ecc-engine = <&bch>;



		nand@1 {

			reg = <1>;
@@ -67,14 +70,17 @@ nemc: nemc@13410000 { 
	};

};



The BCH controller is a separate SoC component used for error correction on

The ECC controller is a separate SoC component used for error correction on

NAND devices. The following is a description of the device properties for a

BCH controller.



Required BCH properties:

- compatible: Should be set to "ingenic,jz4780-bch".

- reg: Should specify the BCH controller registers location and length.

- clocks: Clock for the BCH controller.

ECC controller.



Required ECC properties:

- compatible: Should be one of:

  * ingenic,jz4740-ecc

  * ingenic,jz4725b-bch

  * ingenic,jz4780-bch

- reg: Should specify the ECC controller registers location and length.

- clocks: Clock for the ECC controller.



Example:

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