Commit 4d9e01da authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next 



Jeff Kirsher says:

====================
This series contains updates to e1000e and ixgbe.  Majority of the patches
are against e1000e, where Bruce makes several cosmetic #define moves into
header files.  In addition, Bruce does a cleanup of braces to resolve
checkpatch warnings (when using the strict option).

Ixgbe patches contain several fixes as well as updating the copyright.  The
fixes from Josh Hay, resolved a possible NULL pointer dereference and
resolved Smatch warnings by fixing return values and memcpy parameters.
Alex provides 2 fixes, the first is to replace rmb() with
read_barrier_depends() in the Tx cleanup.  The second fixes an MTU
warning when using SR-IOV which corrects the fact that we were using 1522
to test for the max frame size in ixgbe_change_mtu and 1518 in
ixgbe_set_vf_lpe.  The difference was the addition of VLAN_HLEN, which we
only need to add in the case of computing a buffer size, but not a filter
size.  Lastly, a patch from Emil which is based on a community patch from
Aurélien Guillaume which adds functions needed for reading SFF-8472
diagnostic data from SFP modules.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents ca2eb567 c560451c

drivers/net/ethernet/intel/e1000e/80003es2lan.c

+0 −63
Original line number Diff line number Diff line
@@ -32,69 +32,6 @@ 


#include "e1000.h"



#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL	 0x00

#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL	 0x02

#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL	 0x10

#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE	 0x1F



#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS	 0x0008

#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS	 0x0800

#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING	 0x0010



#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004

#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT	 0x0000

#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE		 0x2000



#define E1000_KMRNCTRLSTA_OPMODE_MASK		 0x000C

#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO	 0x0004



#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */

#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN	 0x00010000



#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN	 0x8

#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN	 0x9



/* GG82563 PHY Specific Status Register (Page 0, Register 16 */

#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE	 0x0002 /* 1=Reversal Disab. */

#define GG82563_PSCR_CROSSOVER_MODE_MASK	 0x0060

#define GG82563_PSCR_CROSSOVER_MODE_MDI		 0x0000 /* 00=Manual MDI */

#define GG82563_PSCR_CROSSOVER_MODE_MDIX	 0x0020 /* 01=Manual MDIX */

#define GG82563_PSCR_CROSSOVER_MODE_AUTO	 0x0060 /* 11=Auto crossover */



/* PHY Specific Control Register 2 (Page 0, Register 26) */

#define GG82563_PSCR2_REVERSE_AUTO_NEG		 0x2000

						/* 1=Reverse Auto-Negotiation */



/* MAC Specific Control Register (Page 2, Register 21) */

/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */

#define GG82563_MSCR_TX_CLK_MASK		 0x0007

#define GG82563_MSCR_TX_CLK_10MBPS_2_5		 0x0004

#define GG82563_MSCR_TX_CLK_100MBPS_25		 0x0005

#define GG82563_MSCR_TX_CLK_1000MBPS_25		 0x0007



#define GG82563_MSCR_ASSERT_CRS_ON_TX		 0x0010 /* 1=Assert */



/* DSP Distance Register (Page 5, Register 26) */

#define GG82563_DSPD_CABLE_LENGTH		 0x0007 /* 0 = <50M

							   1 = 50-80M

							   2 = 80-110M

							   3 = 110-140M

							   4 = >140M

							*/



/* Kumeran Mode Control Register (Page 193, Register 16) */

#define GG82563_KMCR_PASS_FALSE_CARRIER		 0x0800



/* Max number of times Kumeran read/write should be validated */

#define GG82563_MAX_KMRN_RETRY  0x5



/* Power Management Control Register (Page 193, Register 20) */

#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE	 0x0001

					   /* 1=Enable SERDES Electrical Idle */



/* In-Band Control Register (Page 194, Register 18) */

#define GG82563_ICR_DIS_PADDING			 0x0010 /* Disable Padding */



/* A table for the GG82563 cable length where the range is defined

 * with a lower bound at "index" and the upper bound at

 * "index + 5".

drivers/net/ethernet/intel/e1000e/80003es2lan.h

0 → 100644
+95 −0
Original line number Diff line number Diff line 
/*******************************************************************************



  Intel PRO/1000 Linux driver

  Copyright(c) 1999 - 2013 Intel Corporation.



  This program is free software; you can redistribute it and/or modify it

  under the terms and conditions of the GNU General Public License,

  version 2, as published by the Free Software Foundation.



  This program is distributed in the hope it will be useful, but WITHOUT

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

  more details.



  You should have received a copy of the GNU General Public License along with

  this program; if not, write to the Free Software Foundation, Inc.,

  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.



  The full GNU General Public License is included in this distribution in

  the file called "COPYING".



  Contact Information:

  Linux NICS <linux.nics@intel.com>

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497



*******************************************************************************/



#ifndef _E1000E_80003ES2LAN_H_

#define _E1000E_80003ES2LAN_H_



#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL	0x00

#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL	0x02

#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL	0x10

#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE	0x1F



#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS	0x0008

#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS	0x0800

#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING	0x0010



#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004

#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT	0x0000

#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE		0x2000



#define E1000_KMRNCTRLSTA_OPMODE_MASK		0x000C

#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO	0x0004



#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00	/* Gig Carry Extend Padding */

#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN	0x00010000



#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN	0x8

#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN	0x9



/* GG82563 PHY Specific Status Register (Page 0, Register 16 */

#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE	0x0002	/* 1=Reversal Dis */

#define GG82563_PSCR_CROSSOVER_MODE_MASK	0x0060

#define GG82563_PSCR_CROSSOVER_MODE_MDI		0x0000	/* 00=Manual MDI */

#define GG82563_PSCR_CROSSOVER_MODE_MDIX	0x0020	/* 01=Manual MDIX */

#define GG82563_PSCR_CROSSOVER_MODE_AUTO	0x0060	/* 11=Auto crossover */



/* PHY Specific Control Register 2 (Page 0, Register 26) */

#define GG82563_PSCR2_REVERSE_AUTO_NEG		0x2000	/* 1=Reverse Auto-Neg */



/* MAC Specific Control Register (Page 2, Register 21) */

/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */

#define GG82563_MSCR_TX_CLK_MASK		0x0007

#define GG82563_MSCR_TX_CLK_10MBPS_2_5		0x0004

#define GG82563_MSCR_TX_CLK_100MBPS_25		0x0005

#define GG82563_MSCR_TX_CLK_1000MBPS_25		0x0007



#define GG82563_MSCR_ASSERT_CRS_ON_TX		0x0010	/* 1=Assert */



/* DSP Distance Register (Page 5, Register 26)

 * 0 = <50M

 * 1 = 50-80M

 * 2 = 80-100M

 * 3 = 110-140M

 * 4 = >140M

 */

#define GG82563_DSPD_CABLE_LENGTH		0x0007



/* Kumeran Mode Control Register (Page 193, Register 16) */

#define GG82563_KMCR_PASS_FALSE_CARRIER		0x0800



/* Max number of times Kumeran read/write should be validated */

#define GG82563_MAX_KMRN_RETRY			0x5



/* Power Management Control Register (Page 193, Register 20) */

/* 1=Enable SERDES Electrical Idle */

#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE	0x0001



/* In-Band Control Register (Page 194, Register 18) */

#define GG82563_ICR_DIS_PADDING			0x0010	/* Disable Padding */



#endif

drivers/net/ethernet/intel/e1000e/82571.c

+0 −16
Original line number Diff line number Diff line
@@ -44,21 +44,6 @@ 


#include "e1000.h"



#define ID_LED_RESERVED_F746 0xF746

#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \

			      (ID_LED_OFF1_ON2  <<  8) | \

			      (ID_LED_DEF1_DEF2 <<  4) | \

			      (ID_LED_DEF1_DEF2))



#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000

#define AN_RETRY_COUNT          5 /* Autoneg Retry Count value */

#define E1000_BASE1000T_STATUS          10

#define E1000_IDLE_ERROR_COUNT_MASK     0xFF

#define E1000_RECEIVE_ERROR_COUNTER     21

#define E1000_RECEIVE_ERROR_MAX         0xFFFF



#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */



static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);

static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);

static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
@@ -1549,7 +1534,6 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 
	rxcw = er32(RXCW);



	if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {



		/* Receiver is synchronized with no invalid bits.  */

		switch (mac->serdes_link_state) {

		case e1000_serdes_link_autoneg_complete:

drivers/net/ethernet/intel/e1000e/82571.h

0 → 100644
+58 −0
Original line number Diff line number Diff line 
/*******************************************************************************



  Intel PRO/1000 Linux driver

  Copyright(c) 1999 - 2013 Intel Corporation.



  This program is free software; you can redistribute it and/or modify it

  under the terms and conditions of the GNU General Public License,

  version 2, as published by the Free Software Foundation.



  This program is distributed in the hope it will be useful, but WITHOUT

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

  more details.



  You should have received a copy of the GNU General Public License along with

  this program; if not, write to the Free Software Foundation, Inc.,

  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.



  The full GNU General Public License is included in this distribution in

  the file called "COPYING".



  Contact Information:

  Linux NICS <linux.nics@intel.com>

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497



*******************************************************************************/



#ifndef _E1000E_82571_H_

#define _E1000E_82571_H_



#define ID_LED_RESERVED_F746	0xF746

#define ID_LED_DEFAULT_82573	((ID_LED_DEF1_DEF2 << 12) | \

				 (ID_LED_OFF1_ON2  <<  8) | \

				 (ID_LED_DEF1_DEF2 <<  4) | \

				 (ID_LED_DEF1_DEF2))



#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX	0x08000000

#define AN_RETRY_COUNT		5	/* Autoneg Retry Count value */



/* Intr Throttling - RW */

#define E1000_EITR_82574(_n)	(0x000E8 + (0x4 * (_n)))



#define E1000_EIAC_82574	0x000DC	/* Ext. Interrupt Auto Clear - RW */

#define E1000_EIAC_MASK_82574	0x01F00000



/* Manageability Operation Mode mask */

#define E1000_NVM_INIT_CTRL2_MNGM	0x6000



#define E1000_BASE1000T_STATUS		10

#define E1000_IDLE_ERROR_COUNT_MASK	0xFF

#define E1000_RECEIVE_ERROR_COUNTER	21

#define E1000_RECEIVE_ERROR_MAX		0xFFFF

bool e1000_check_phy_82574(struct e1000_hw *hw);

bool e1000e_get_laa_state_82571(struct e1000_hw *hw);

void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);



#endif

drivers/net/ethernet/intel/e1000e/defines.h

+0 −38
Original line number Diff line number Diff line
@@ -606,8 +606,6 @@ 
#define NVM_ALT_MAC_ADDR_PTR       0x0037

#define NVM_CHECKSUM_REG           0x003F



#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */



#define E1000_NVM_CFG_DONE_PORT_0  0x40000 /* MNG config cycle done */

#define E1000_NVM_CFG_DONE_PORT_1  0x80000 /* ...for second port */
@@ -751,38 +749,6 @@ 
/* BME1000 PHY Specific Control Register */

#define BME1000_PSCR_ENABLE_DOWNSHIFT   0x0800 /* 1 = enable downshift */



/* PHY Low Power Idle Control */

#define I82579_LPI_CTRL				PHY_REG(772, 20)

#define I82579_LPI_CTRL_100_ENABLE		0x2000

#define I82579_LPI_CTRL_1000_ENABLE		0x4000

#define I82579_LPI_CTRL_ENABLE_MASK		0x6000

#define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT	0x80



/* Extended Management Interface (EMI) Registers */

#define I82579_EMI_ADDR		0x10

#define I82579_EMI_DATA		0x11

#define I82579_LPI_UPDATE_TIMER	0x4805	/* in 40ns units + 40 ns base value */

#define I82579_MSE_THRESHOLD	0x084F	/* 82579 Mean Square Error Threshold */

#define I82577_MSE_THRESHOLD	0x0887	/* 82577 Mean Square Error Threshold */

#define I82579_MSE_LINK_DOWN	0x2411	/* MSE count before dropping link */

#define I82579_EEE_PCS_STATUS	0x182D	/* IEEE MMD Register 3.1 >> 8 */

#define I82579_EEE_CAPABILITY	0x0410	/* IEEE MMD Register 3.20 */

#define I82579_EEE_ADVERTISEMENT	0x040E	/* IEEE MMD Register 7.60 */

#define I82579_EEE_LP_ABILITY		0x040F	/* IEEE MMD Register 7.61 */

#define I82579_EEE_100_SUPPORTED	(1 << 1) /* 100BaseTx EEE supported */

#define I82579_EEE_1000_SUPPORTED	(1 << 2) /* 1000BaseTx EEE supported */

#define I217_EEE_PCS_STATUS	0x9401	/* IEEE MMD Register 3.1 */

#define I217_EEE_CAPABILITY	0x8000	/* IEEE MMD Register 3.20 */

#define I217_EEE_ADVERTISEMENT	0x8001	/* IEEE MMD Register 7.60 */

#define I217_EEE_LP_ABILITY	0x8002	/* IEEE MMD Register 7.61 */



#define E1000_EEE_RX_LPI_RCVD	0x0400	/* Tx LP idle received */

#define E1000_EEE_TX_LPI_RCVD	0x0800	/* Rx LP idle received */



#define PHY_PAGE_SHIFT 5

#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \

                           ((reg) & MAX_PHY_REG_ADDRESS))



/* Bits...

 * 15-5: page

 * 4-0: register offset
@@ -829,8 +795,4 @@ 
/* SerDes Control */

#define E1000_GEN_POLL_TIMEOUT          640



/* FW Semaphore */

#define E1000_FWSM_WLOCK_MAC_MASK	0x0380

#define E1000_FWSM_WLOCK_MAC_SHIFT	7



#endif /* _E1000_DEFINES_H_ */

CRA Git | Maintained and supported by SUSTech CRA and CCSE