Commit 4d9d54a7 authored by Tomi Valkeinen's avatar Tomi Valkeinen Committed by Andrzej Hajda
Browse files

drm/bridge: tc358767: fix single lane configuration 



PHY_2LANE bit is always set in DP_PHY_CTRL, breaking 1 lane use.

Set PHY_2LANE only when 2 lanes are used.

Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190103115954.12785-4-tomi.valkeinen@ti.com
parent adf41098

drivers/gpu/drm/bridge/tc358767.c

+8 −2
Original line number Diff line number Diff line
@@ -543,6 +543,7 @@ static int tc_aux_link_setup(struct tc_data *tc) 
	unsigned long rate;

	u32 value;

	int ret;

	u32 dp_phy_ctrl;



	rate = clk_get_rate(tc->refclk);

	switch (rate) {
@@ -567,7 +568,10 @@ static int tc_aux_link_setup(struct tc_data *tc) 
	value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;

	tc_write(SYS_PLLPARAM, value);



	tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | PHY_2LANE | PHY_A0_EN);

	dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN;

	if (tc->link.base.num_lanes == 2)

		dp_phy_ctrl |= PHY_2LANE;

	tc_write(DP_PHY_CTRL, dp_phy_ctrl);



	/*

	 * Initially PLLs are in bypass. Force PLL parameter update,
@@ -860,7 +864,9 @@ static int tc_main_link_setup(struct tc_data *tc) 
	tc_write(SYS_PLLPARAM, value);



	/* Setup Main Link */

	dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_2LANE | PHY_A0_EN |  PHY_M0_EN;

	dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;

	if (tc->link.base.num_lanes == 2)

		dp_phy_ctrl |= PHY_2LANE;

	tc_write(DP_PHY_CTRL, dp_phy_ctrl);

	msleep(100);

CRA Git | Maintained and supported by SUSTech CRA and CCSE