Commit 4d8fb494 authored by Miquel Raynal's avatar Miquel Raynal Committed by Stephen Boyd
Browse files

clk: mvebu: armada-37xx-periph: add PCIe gated clock 



The PCIe clock is a gated clock which has the same source as GbE0
(both IPs share a set of registers). This source clock is called
'gbe_core' in the driver.

Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190627125245.26788-2-miquel.raynal@bootlin.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 54ecb8f7

drivers/clk/mvebu/armada-37xx-periph.c

+2 −0
Original line number Diff line number Diff line
@@ -303,6 +303,7 @@ PERIPH_CLK_GATE_DIV(gbe_bm, 12, DIV_SEL1, 0, clk_table1); 
PERIPH_CLK_FULL_DD(sdio, 11, 14, DIV_SEL0, DIV_SEL0, 3, 6);

PERIPH_CLK_FULL_DD(usb32_usb2_sys, 16, 16, DIV_SEL0, DIV_SEL0, 9, 12);

PERIPH_CLK_FULL_DD(usb32_ss_sys, 17, 18, DIV_SEL0, DIV_SEL0, 15, 18);

static PERIPH_GATE(pcie, 14);



static struct clk_periph_data data_sb[] = {

	REF_CLK_MUX_DD(gbe_50),
@@ -318,6 +319,7 @@ static struct clk_periph_data data_sb[] = { 
	REF_CLK_FULL_DD(sdio),

	REF_CLK_FULL_DD(usb32_usb2_sys),

	REF_CLK_FULL_DD(usb32_ss_sys),

	REF_CLK_GATE(pcie, "gbe_core"),

	{ },

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE