dt-bindings: net: dp83869: Add TI dp83869 phy

# SPDX-License-Identifier: GPL-2.0

# Copyright (C) 2019 Texas Instruments Incorporated

%YAML 1.2

---

$id: "http://devicetree.org/schemas/net/ti,dp83869.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: TI DP83869 ethernet PHY

allOf:

  - $ref: "ethernet-controller.yaml#"

maintainers:

  - Dan Murphy <dmurphy@ti.com>

description: |

  The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver

  with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and

  1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and

  100BASE-FX Fiber protocols.

  This device interfaces to the MAC layer through Reduced GMII (RGMII) and

  SGMII The DP83869HM supports Media Conversion in Managed mode. In this mode,

  the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX

  conversions.  The DP83869HM can also support Bridge Conversion from RGMII to

  SGMII and SGMII to RGMII.

  Specifications about the charger can be found at:

    http://www.ti.com/lit/ds/symlink/dp83869hm.pdf

properties:

  reg:

    maxItems: 1

  ti,min-output-impedance:

    type: boolean

    description: |

       MAC Interface Impedance control to set the programmable output impedance

       to a minimum value (35 ohms).

  ti,max-output-impedance:

    type: boolean

    description: |

       MAC Interface Impedance control to set the programmable output impedance

       to a maximum value (70 ohms).

  tx-fifo-depth:

    $ref: /schemas/types.yaml#definitions/uint32

    description: |

       Transmitt FIFO depth see dt-bindings/net/ti-dp83869.h for values

  rx-fifo-depth:

    $ref: /schemas/types.yaml#definitions/uint32

    description: |

       Receive FIFO depth see dt-bindings/net/ti-dp83869.h for values

  ti,clk-output-sel:

    $ref: /schemas/types.yaml#definitions/uint32

    description: |

       Muxing option for CLK_OUT pin see dt-bindings/net/ti-dp83869.h for values.

  ti,op-mode:

    $ref: /schemas/types.yaml#definitions/uint32

    description: |

       Operational mode for the PHY.  If this is not set then the operational

       mode is set by the straps. see dt-bindings/net/ti-dp83869.h for values

required:

  - reg

examples:

  - |

    #include <dt-bindings/net/ti-dp83869.h>

    mdio0 {

      #address-cells = <1>;

      #size-cells = <0>;

      ethphy0: ethernet-phy@0 {

        reg = <0>;

        tx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;

        rx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;

        ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;

        ti,max-output-impedance = "true";

        ti,clk-output-sel = <DP83869_CLK_O_SEL_CHN_A_RCLK>;

      };

    };

/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Device Tree constants for the Texas Instruments DP83869 PHY

 *

 * Author: Dan Murphy <dmurphy@ti.com>

 *

 * Copyright:   (C) 2019 Texas Instruments, Inc.

 */

#ifndef _DT_BINDINGS_TI_DP83869_H

#define _DT_BINDINGS_TI_DP83869_H

/* PHY CTRL bits */

#define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB	0x00

#define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB	0x01

#define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB	0x02

#define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB	0x03

/* IO_MUX_CFG - Clock output selection */

#define DP83869_CLK_O_SEL_CHN_A_RCLK		0x0

#define DP83869_CLK_O_SEL_CHN_B_RCLK		0x1

#define DP83869_CLK_O_SEL_CHN_C_RCLK		0x2

#define DP83869_CLK_O_SEL_CHN_D_RCLK		0x3

#define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5	0x4

#define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5	0x5

#define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5	0x6

#define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5	0x7

#define DP83869_CLK_O_SEL_CHN_A_TCLK		0x8

#define DP83869_CLK_O_SEL_CHN_B_TCLK		0x9

#define DP83869_CLK_O_SEL_CHN_C_TCLK		0xa

#define DP83869_CLK_O_SEL_CHN_D_TCLK		0xb

#define DP83869_CLK_O_SEL_REF_CLK		0xc

#define DP83869_RGMII_COPPER_ETHERNET		0x00

#define DP83869_RGMII_1000_BASE			0x01

#define DP83869_RGMII_100_BASE			0x02

#define DP83869_RGMII_SGMII_BRIDGE		0x03

#define DP83869_1000M_MEDIA_CONVERT		0x04

#define DP83869_100M_MEDIA_CONVERT		0x05

#define DP83869_SGMII_COPPER_ETHERNET		0x06

#endif