Commit 4d64556b authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-v4.14-samsung' of... 

Merge tag 'clk-v4.14-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next

Pull Samsung clk driver updates from Sylwester Nawrocki:

Changes in definitions of audio related clocks for Exynos5420/5422/5800
SoCs: a fix of mau_epll clock definition and changes enabling clock rate
setting propagation on a path from the I2S IP block up the EPLL.

* tag 'clk-v4.14-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
  clk: samsung: exynos542x: Enable clock rate propagation up to the EPLL
  clk: samsung: Add CLK_SET_RATE_PARENT to some AUDSS CLK CON clocks
  clk: samsung: Fix mau_epll clock definition for exynos5422
parents 3477a72b 599cebea

drivers/clk/samsung/clk-exynos-audss.c

+4 −4
Original line number Diff line number Diff line
@@ -180,7 +180,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) 
	}

	clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss",

				mout_audss_p, ARRAY_SIZE(mout_audss_p),

				CLK_SET_RATE_NO_REPARENT,

				CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,

				reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);



	cdclk = devm_clk_get(&pdev->dev, "cdclk");
@@ -195,11 +195,11 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) 
				reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);



	clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(NULL, "dout_srp",

				"mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,

				0, &lock);

				"mout_audss", CLK_SET_RATE_PARENT,

				reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);



	clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(NULL,

				"dout_aud_bus", "dout_srp", 0,

				"dout_aud_bus", "dout_srp", CLK_SET_RATE_PARENT,

				reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);



	clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(NULL, "dout_i2s",

drivers/clk/samsung/clk-exynos5420.c

+15 −8
Original line number Diff line number Diff line
@@ -537,8 +537,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { 


	MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",

			mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2),

	MUX(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,

							SRC_TOP7, 20, 2),

	MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,

			SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),

	MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),

	MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
@@ -547,8 +547,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { 
	MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),

	MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),



	MUX(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,

							SRC_TOP9, 8, 1),

	MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,

			SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),

	MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,

							SRC_TOP9, 16, 1),

	MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
@@ -590,6 +590,8 @@ static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = { 
				GATE_BUS_TOP, 24, 0, 0),

	GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",

				GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),

	GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll",

			SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),

};



static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
@@ -629,6 +631,11 @@ static const struct samsung_div_clock exynos5420_div_clks[] __initconst = { 
			"mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),

};



static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {

	GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",

			SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),

};



static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {

	MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,

			SRC_TOP7, 4, 1),
@@ -706,7 +713,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { 
	MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),

	MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),

	MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),

	MUX(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1),

	MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,

			CLK_SET_RATE_PARENT, 0),

	MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),

	MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
@@ -1001,9 +1009,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { 
	GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",

			SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0),



	GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",

			SRC_MASK_TOP7, 20, 0, 0),



	/* sclk */

	GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",

		GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
@@ -1440,6 +1445,8 @@ static void __init exynos5x_clk_init(struct device_node *np, 
				ARRAY_SIZE(exynos5420_mux_clks));

		samsung_clk_register_div(ctx, exynos5420_div_clks,

				ARRAY_SIZE(exynos5420_div_clks));

		samsung_clk_register_gate(ctx, exynos5420_gate_clks,

				ARRAY_SIZE(exynos5420_gate_clks));

	} else {

		samsung_clk_register_fixed_factor(

				ctx, exynos5800_fixed_factor_clks,

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