drm/amd/display: Add DCN3 CLK_MGR

AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN21)

endif

ifdef CONFIG_DRM_AMD_DC_DCN3_0

###############################################################################

# DCN30

###############################################################################

CLK_MGR_DCN30 = dcn30_clk_mgr.o dcn30_clk_mgr_smu_msg.o

AMD_DAL_CLK_MGR_DCN30 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn30/,$(CLK_MGR_DCN30))

AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN30)

endif

#include "dcn10/rv2_clk_mgr.h"

#include "dcn20/dcn20_clk_mgr.h"

#include "dcn21/rn_clk_mgr.h"

#if defined(CONFIG_DRM_AMD_DC_DCN3_0)

#include "dcn30/dcn30_clk_mgr.h"

#endif

int clk_mgr_helper_get_active_display_cnt(

		break;

	case FAMILY_NV:

#if defined(CONFIG_DRM_AMD_DC_DCN3_0)

		if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) {

			/* TODO: to add SIENNA_CICHLID clk_mgr support, once CLK IP header files are available,

			 * for now use DCN3AG clk mgr.

			 */

			dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

			break;

		}

#endif

		dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

		break;

#endif	/* Family RV and NV*/

void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)

{

	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

#ifdef CONFIG_DRM_AMD_DC_DCN3_0

	switch (clk_mgr_base->ctx->asic_id.chip_family) {

	case FAMILY_NV:

		if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {

			dcn3_clk_mgr_destroy(clk_mgr);

			break;

		}

	}

#endif

	kfree(clk_mgr);

}

/*

 * Copyright 2020 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */

// TEMPORARY until this exists in the proper location

#ifndef DALSMC_H

#define DALSMC_H

#define DALSMC_VERSION 0x1

// SMU Response Codes:

#define DALSMC_Result_OK                   0x1

#define DALSMC_Result_Failed               0xFF

#define DALSMC_Result_UnknownCmd           0xFE

#define DALSMC_Result_CmdRejectedPrereq    0xFD

#define DALSMC_Result_CmdRejectedBusy      0xFC

// Message Definitions:

#define DALSMC_MSG_TestMessage                    0x1

#define DALSMC_MSG_GetSmuVersion                  0x2

#define DALSMC_MSG_GetDriverIfVersion             0x3

#define DALSMC_MSG_GetMsgHeaderVersion            0x4

#define DALSMC_MSG_SetDalDramAddrHigh             0x5

#define DALSMC_MSG_SetDalDramAddrLow              0x6

#define DALSMC_MSG_TransferTableSmu2Dram          0x7

#define DALSMC_MSG_TransferTableDram2Smu          0x8

#define DALSMC_MSG_SetHardMinByFreq               0x9

#define DALSMC_MSG_SetHardMaxByFreq               0xA

#define DALSMC_MSG_GetDpmFreqByIndex              0xB

#define DALSMC_MSG_GetDcModeMaxDpmFreq            0xC

#define DALSMC_MSG_SetMinDeepSleepDcefclk         0xD

#define DALSMC_MSG_NumOfDisplays                  0xE

#define DALSMC_MSG_SetExternalClientDfCstateAllow 0x10

#define DALSMC_MSG_BacoAudioD3PME                 0x11

#define DALSMC_Message_Count                      0x12

#endif