Commit 4d4585c2 authored by Viresh Kumar's avatar Viresh Kumar Committed by Wei Xu
Browse files

arm64: dts: hisilicon: Add missing cooling device properties for CPUs 



The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.

Add such missing properties.

Do minor rearrangement as well to keep ordering consistent.

Signed-off-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: default avatarWei Xu <xuwei5@hisilicon.com>
parent a5956def

arch/arm64/boot/dts/hisilicon/hi6220.dtsi

+15 −1
Original line number Diff line number Diff line
@@ -88,8 +88,8 @@ 
			next-level-cache = <&CLUSTER0_L2>;

			clocks = <&stub_clock 0>;

			operating-points-v2 = <&cpu_opp_table>;

			#cooling-cells = <2>; /* min followed by max */

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

			#cooling-cells = <2>; /* min followed by max */

			dynamic-power-coefficient = <311>;

		};
@@ -101,6 +101,8 @@ 
			next-level-cache = <&CLUSTER0_L2>;

			operating-points-v2 = <&cpu_opp_table>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

			#cooling-cells = <2>; /* min followed by max */

			dynamic-power-coefficient = <311>;

		};



		cpu2: cpu@2 {
@@ -111,6 +113,8 @@ 
			next-level-cache = <&CLUSTER0_L2>;

			operating-points-v2 = <&cpu_opp_table>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

			#cooling-cells = <2>; /* min followed by max */

			dynamic-power-coefficient = <311>;

		};



		cpu3: cpu@3 {
@@ -121,6 +125,8 @@ 
			next-level-cache = <&CLUSTER0_L2>;

			operating-points-v2 = <&cpu_opp_table>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

			#cooling-cells = <2>; /* min followed by max */

			dynamic-power-coefficient = <311>;

		};



		cpu4: cpu@100 {
@@ -131,6 +137,8 @@ 
			next-level-cache = <&CLUSTER1_L2>;

			operating-points-v2 = <&cpu_opp_table>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

			#cooling-cells = <2>; /* min followed by max */

			dynamic-power-coefficient = <311>;

		};



		cpu5: cpu@101 {
@@ -141,6 +149,8 @@ 
			next-level-cache = <&CLUSTER1_L2>;

			operating-points-v2 = <&cpu_opp_table>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

			#cooling-cells = <2>; /* min followed by max */

			dynamic-power-coefficient = <311>;

		};



		cpu6: cpu@102 {
@@ -151,6 +161,8 @@ 
			next-level-cache = <&CLUSTER1_L2>;

			operating-points-v2 = <&cpu_opp_table>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

			#cooling-cells = <2>; /* min followed by max */

			dynamic-power-coefficient = <311>;

		};



		cpu7: cpu@103 {
@@ -161,6 +173,8 @@ 
			next-level-cache = <&CLUSTER1_L2>;

			operating-points-v2 = <&cpu_opp_table>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

			#cooling-cells = <2>; /* min followed by max */

			dynamic-power-coefficient = <311>;

		};



		CLUSTER0_L2: l2-cache0 {

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