Merge branch 'for-4.2/ti-clk-move' of https://github.com/t-kristo/linux-pm into clk-next (4d341056) · Commits · 戴 / test

arch/arm/mach-omap2/Makefile

+7 −15

Original line number	Diff line number	Diff line
		@@ -12,8 +12,7 @@ obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o timer.o pm.o \

		hwmod-common = omap_hwmod.o omap_hwmod_reset.o \
		omap_hwmod_common_data.o
		clock-common = clock.o clock_common_data.o \
		clkt_dpll.o clkt_clksel.o
		clock-common = clock.o
		secure-common = omap-smc.o omap-secure.o

		obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
		@@ -182,24 +181,17 @@ obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common)
		obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o

		# Clock framework
		obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
		obj-$(CONFIG_ARCH_OMAP2) += $(clock-common)
		obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
		obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
		obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o
		obj-$(CONFIG_SOC_OMAP2430) += clock2430.o
		obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
		obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
		obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
		obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o
		obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
		obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o
		obj-$(CONFIG_ARCH_OMAP3) += $(clock-common)
		obj-$(CONFIG_ARCH_OMAP3) += clkt34xx_dpll3m2.o
		obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
		obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
		obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
		obj-$(CONFIG_SOC_AM33XX) += $(clock-common)
		obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
		obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
		obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
		obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o
		obj-$(CONFIG_SOC_AM43XX) += $(clock-common) dpll3xxx.o
		obj-$(CONFIG_SOC_AM43XX) += $(clock-common)

		# OMAP2 clock rate set data (old "OPP" data)
		obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o

arch/arm/mach-omap2/clkt34xx_dpll3m2.c

+5 −2

Original line number	Diff line number	Diff line
		@@ -23,12 +23,13 @@

		#include "clock.h"
		#include "clock3xxx.h"
		#include "clock34xx.h"
		#include "sdrc.h"
		#include "sram.h"

		#define CYCLES_PER_MHZ 1000000

		struct clk sdrc_ick_p, arm_fck_p;

		/*
		* CORE DPLL (DPLL3) M2 divider rate programming functions
		*
		@@ -60,7 +61,9 @@ int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate,
		if (!clk \|\| !rate)
		return -EINVAL;

		validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
		new_div = DIV_ROUND_UP(parent_rate, rate);
		validrate = parent_rate / new_div;

		if (validrate != rate)
		return -EINVAL;

arch/arm/mach-omap2/clkt_clksel.c

deleted100644 → 0

+0 −466

Original line number	Diff line number	Diff line
		/*
		* clkt_clksel.c - OMAP2/3/4 clksel clock functions
		*
		* Copyright (C) 2005-2008 Texas Instruments, Inc.
		* Copyright (C) 2004-2010 Nokia Corporation
		*
		* Contacts:
		* Richard Woodruff <r-woodruff2@ti.com>
		* Paul Walmsley
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*
		*
		* clksel clocks are clocks that do not have a fixed parent, or that
		* can divide their parent's rate, or possibly both at the same time, based
		* on the contents of a hardware register bitfield.
		*
		* All of the various mux and divider settings can be encoded into
		* struct clksel* data structures, and then these can be autogenerated
		* from some hardware database for each new chip generation. This
		* should avoid the need to write, review, and validate a lot of new
		* clock code for each new chip, since it can be exported from the SoC
		* design flow. This is now done on OMAP4.
		*
		* The fusion of mux and divider clocks is a software creation. In
		* hardware reality, the multiplexer (parent selection) and the
		* divider exist separately. XXX At some point these clksel clocks
		* should be split into "divider" clocks and "mux" clocks to better
		* match the hardware.
		*
		* (The name "clksel" comes from the name of the corresponding
		* register field in the OMAP2/3 family of SoCs.)
		*
		* XXX Currently these clocks are only used in the OMAP2/3/4 code, but
		* many of the OMAP1 clocks should be convertible to use this
		* mechanism.
		*/
		#undef DEBUG

		#include <linux/kernel.h>
		#include <linux/errno.h>
		#include <linux/clk-provider.h>
		#include <linux/io.h>
		#include <linux/bug.h>

		#include "clock.h"

		/* Private functions */

		/**
		* _get_clksel_by_parent() - return clksel struct for a given clk & parent
		* @clk: OMAP struct clk ptr to inspect
		* @src_clk: OMAP struct clk ptr of the parent clk to search for
		*
		* Scan the struct clksel array associated with the clock to find
		* the element associated with the supplied parent clock address.
		* Returns a pointer to the struct clksel on success or NULL on error.
		*/
		static const struct clksel _get_clksel_by_parent(struct clk_hw_omap clk,
		struct clk *src_clk)
		{
		const struct clksel *clks;

		if (!src_clk)
		return NULL;

		for (clks = clk->clksel; clks->parent; clks++)
		if (clks->parent == src_clk)
		break; /* Found the requested parent */

		if (!clks->parent) {
		/* This indicates a data problem */
		WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
		__clk_get_name(clk->hw.clk), __clk_get_name(src_clk));
		return NULL;
		}

		return clks;
		}

		/**
		* _write_clksel_reg() - program a clock's clksel register in hardware
		* @clk: struct clk * to program
		* @v: clksel bitfield value to program (with LSB at bit 0)
		*
		* Shift the clksel register bitfield value @v to its appropriate
		* location in the clksel register and write it in. This function
		* will ensure that the write to the clksel_reg reaches its
		* destination before returning -- important since PRM and CM register
		* accesses can be quite slow compared to ARM cycles -- but does not
		* take into account any time the hardware might take to switch the
		* clock source.
		*/
		static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val)
		{
		u32 v;

		v = omap2_clk_readl(clk, clk->clksel_reg);
		v &= ~clk->clksel_mask;
		v \|= field_val << __ffs(clk->clksel_mask);
		omap2_clk_writel(v, clk, clk->clksel_reg);

		v = omap2_clk_readl(clk, clk->clksel_reg); /* OCP barrier */
		}

		/**
		* _clksel_to_divisor() - turn clksel field value into integer divider
		* @clk: OMAP struct clk to use
		* @field_val: register field value to find
		*
		* Given a struct clk of a rate-selectable clksel clock, and a register field
		* value to search for, find the corresponding clock divisor. The register
		* field value should be pre-masked and shifted down so the LSB is at bit 0
		* before calling. Returns 0 on error or returns the actual integer divisor
		* upon success.
		*/
		static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val)
		{
		const struct clksel *clks;
		const struct clksel_rate *clkr;
		struct clk *parent;

		parent = __clk_get_parent(clk->hw.clk);

		clks = _get_clksel_by_parent(clk, parent);
		if (!clks)
		return 0;

		for (clkr = clks->rates; clkr->div; clkr++) {
		if (!(clkr->flags & cpu_mask))
		continue;

		if (clkr->val == field_val)
		break;
		}

		if (!clkr->div) {
		/* This indicates a data error */
		WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
		__clk_get_name(clk->hw.clk), field_val,
		__clk_get_name(parent));
		return 0;
		}

		return clkr->div;
		}

		/**
		* _divisor_to_clksel() - turn clksel integer divisor into a field value
		* @clk: OMAP struct clk to use
		* @div: integer divisor to search for
		*
		* Given a struct clk of a rate-selectable clksel clock, and a clock
		* divisor, find the corresponding register field value. Returns the
		* register field value _before_ left-shifting (i.e., LSB is at bit
		* 0); or returns 0xFFFFFFFF (~0) upon error.
		*/
		static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div)
		{
		const struct clksel *clks;
		const struct clksel_rate *clkr;
		struct clk *parent;

		/* should never happen */
		WARN_ON(div == 0);

		parent = __clk_get_parent(clk->hw.clk);
		clks = _get_clksel_by_parent(clk, parent);
		if (!clks)
		return ~0;

		for (clkr = clks->rates; clkr->div; clkr++) {
		if (!(clkr->flags & cpu_mask))
		continue;

		if (clkr->div == div)
		break;
		}

		if (!clkr->div) {
		pr_err("clock: %s: could not find divisor %d for parent %s\n",
		__clk_get_name(clk->hw.clk), div,
		__clk_get_name(parent));
		return ~0;
		}

		return clkr->val;
		}

		/**
		* _read_divisor() - get current divisor applied to parent clock (from hdwr)
		* @clk: OMAP struct clk to use.
		*
		* Read the current divisor register value for @clk that is programmed
		* into the hardware, convert it into the actual divisor value, and
		* return it; or return 0 on error.
		*/
		static u32 _read_divisor(struct clk_hw_omap *clk)
		{
		u32 v;

		if (!clk->clksel \|\| !clk->clksel_mask)
		return 0;

		v = omap2_clk_readl(clk, clk->clksel_reg);
		v &= clk->clksel_mask;
		v >>= __ffs(clk->clksel_mask);

		return _clksel_to_divisor(clk, v);
		}

		/* Public functions */

		/**
		* omap2_clksel_round_rate_div() - find divisor for the given clock and rate
		* @clk: OMAP struct clk to use
		* @target_rate: desired clock rate
		* @new_div: ptr to where we should store the divisor
		*
		* Finds 'best' divider value in an array based on the source and target
		* rates. The divider array must be sorted with smallest divider first.
		* This function is also used by the DPLL3 M2 divider code.
		*
		* Returns the rounded clock rate or returns 0xffffffff on error.
		*/
		u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
		unsigned long target_rate,
		u32 *new_div)
		{
		unsigned long test_rate;
		const struct clksel *clks;
		const struct clksel_rate *clkr;
		u32 last_div = 0;
		struct clk *parent;
		unsigned long parent_rate;
		const char *clk_name;

		parent = __clk_get_parent(clk->hw.clk);
		clk_name = __clk_get_name(clk->hw.clk);
		parent_rate = __clk_get_rate(parent);

		if (!clk->clksel \|\| !clk->clksel_mask)
		return ~0;

		pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
		clk_name, target_rate);

		*new_div = 1;

		clks = _get_clksel_by_parent(clk, parent);
		if (!clks)
		return ~0;

		for (clkr = clks->rates; clkr->div; clkr++) {
		if (!(clkr->flags & cpu_mask))
		continue;

		/* Sanity check */
		if (clkr->div <= last_div)
		pr_err("clock: %s: clksel_rate table not sorted\n",
		clk_name);

		last_div = clkr->div;

		test_rate = parent_rate / clkr->div;

		if (test_rate <= target_rate)
		break; /* found it */
		}

		if (!clkr->div) {
		pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n",
		clk_name, target_rate, __clk_get_name(parent));
		return ~0;
		}

		*new_div = clkr->div;

		pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
		(parent_rate / clkr->div));

		return parent_rate / clkr->div;
		}

		/*
		* Clocktype interface functions to the OMAP clock code
		* (i.e., those used in struct clk field function pointers, etc.)
		*/

		/**
		* omap2_clksel_find_parent_index() - return the array index of the current
		* hardware parent of @hw
		* @hw: struct clk_hw * to find the current hardware parent of
		*
		* Given a struct clk_hw pointer @hw to the 'hw' member of a struct
		* clk_hw_omap record representing a source-selectable hardware clock,
		* read the hardware register and determine what its parent is
		* currently set to. Intended to be called only by the common clock
		* framework struct clk_hw_ops.get_parent function pointer. Return
		* the array index of this parent clock upon success -- there is no
		* way to return an error, so if we encounter an error, just WARN()
		* and pretend that we know that we're doing.
		*/
		u8 omap2_clksel_find_parent_index(struct clk_hw *hw)
		{
		struct clk_hw_omap *clk = to_clk_hw_omap(hw);
		const struct clksel *clks;
		const struct clksel_rate *clkr;
		u32 r, found = 0;
		struct clk *parent;
		const char *clk_name;
		int ret = 0, f = 0;

		parent = __clk_get_parent(hw->clk);
		clk_name = __clk_get_name(hw->clk);

		/* XXX should be able to return an error */
		WARN((!clk->clksel \|\| !clk->clksel_mask),
		"clock: %s: attempt to call on a non-clksel clock", clk_name);

		r = omap2_clk_readl(clk, clk->clksel_reg) & clk->clksel_mask;
		r >>= __ffs(clk->clksel_mask);

		for (clks = clk->clksel; clks->parent && !found; clks++) {
		for (clkr = clks->rates; clkr->div && !found; clkr++) {
		if (!(clkr->flags & cpu_mask))
		continue;

		if (clkr->val == r) {
		found = 1;
		ret = f;
		}
		}
		f++;
		}

		/* This indicates a data error */
		WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
		clk_name, r);

		return ret;
		}


		/**
		* omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field
		* @clk: struct clk *
		*
		* This function is intended to be called only by the clock framework.
		* Each clksel clock should have its struct clk .recalc field set to this
		* function. Returns the clock's current rate, based on its parent's rate
		* and its current divisor setting in the hardware.
		*/
		unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate)
		{
		unsigned long rate;
		u32 div = 0;
		struct clk_hw_omap *clk = to_clk_hw_omap(hw);

		if (!parent_rate)
		return 0;

		div = _read_divisor(clk);
		if (!div)
		rate = parent_rate;
		else
		rate = parent_rate / div;

		pr_debug("%s: recalc'd %s's rate to %lu (div %d)\n", __func__,
		__clk_get_name(hw->clk), rate, div);

		return rate;
		}

		/**
		* omap2_clksel_round_rate() - find rounded rate for the given clock and rate
		* @clk: OMAP struct clk to use
		* @target_rate: desired clock rate
		*
		* This function is intended to be called only by the clock framework.
		* Finds best target rate based on the source clock and possible dividers.
		* rates. The divider array must be sorted with smallest divider first.
		*
		* Returns the rounded clock rate or returns 0xffffffff on error.
		*/
		long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
		unsigned long *parent_rate)
		{
		struct clk_hw_omap *clk = to_clk_hw_omap(hw);
		u32 new_div;

		return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
		}

		/**
		* omap2_clksel_set_rate() - program clock rate in hardware
		* @clk: struct clk * to program rate
		* @rate: target rate to program
		*
		* This function is intended to be called only by the clock framework.
		* Program @clk's rate to @rate in the hardware. The clock can be
		* either enabled or disabled when this happens, although if the clock
		* is enabled, some downstream devices may glitch or behave
		* unpredictably when the clock rate is changed - this depends on the
		* hardware. This function does not currently check the usecount of
		* the clock, so if multiple drivers are using the clock, and the rate
		* is changed, they will all be affected without any notification.
		* Returns -EINVAL upon error, or 0 upon success.
		*/
		int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
		{
		struct clk_hw_omap *clk = to_clk_hw_omap(hw);
		u32 field_val, validrate, new_div = 0;

		if (!clk->clksel \|\| !clk->clksel_mask)
		return -EINVAL;

		validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
		if (validrate != rate)
		return -EINVAL;

		field_val = _divisor_to_clksel(clk, new_div);
		if (field_val == ~0)
		return -EINVAL;

		_write_clksel_reg(clk, field_val);

		pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(hw->clk),
		__clk_get_rate(hw->clk));

		return 0;
		}

		/*
		* Clksel parent setting function - not passed in struct clk function
		* pointer - instead, the OMAP clock code currently assumes that any
		* parent-setting clock is a clksel clock, and calls
		* omap2_clksel_set_parent() by default
		*/

		/**
		* omap2_clksel_set_parent() - change a clock's parent clock
		* @clk: struct clk * of the child clock
		* @new_parent: struct clk * of the new parent clock
		*
		* This function is intended to be called only by the clock framework.
		* Change the parent clock of clock @clk to @new_parent. This is
		* intended to be used while @clk is disabled. This function does not
		* currently check the usecount of the clock, so if multiple drivers
		* are using the clock, and the parent is changed, they will all be
		* affected without any notification. Returns -EINVAL upon error, or
		* 0 upon success.
		*/
		int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val)
		{
		struct clk_hw_omap *clk = to_clk_hw_omap(hw);

		if (!clk->clksel \|\| !clk->clksel_mask)
		return -EINVAL;

		_write_clksel_reg(clk, field_val);
		return 0;
		}

arch/arm/mach-omap2/clock.c

+27 −648

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-omap2/clock.h

+1 −204

Original line number	Diff line number	Diff line
		@@ -23,90 +23,6 @@
		#include <linux/clk-provider.h>
		#include <linux/clk/ti.h>

		struct omap_clk {
		u16 cpu;
		struct clk_lookup lk;
		};

		#define CLK(dev, con, ck) \
		{ \
		.lk = { \
		.dev_id = dev, \
		.con_id = con, \
		.clk = ck, \
		}, \
		}

		struct clockdomain;

		#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
		static struct clk_core _name##_core = { \
		.name = #_name, \
		.hw = &_name##_hw.hw, \
		.parent_names = _parent_array_name, \
		.num_parents = ARRAY_SIZE(_parent_array_name), \
		.ops = &_clkops_name, \
		}; \
		static struct clk _name = { \
		.core = &_name##_core, \
		};

		#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \
		_clkops_name, _flags) \
		static struct clk_core _name##_core = { \
		.name = #_name, \
		.hw = &_name##_hw.hw, \
		.parent_names = _parent_array_name, \
		.num_parents = ARRAY_SIZE(_parent_array_name), \
		.ops = &_clkops_name, \
		.flags = _flags, \
		}; \
		static struct clk _name = { \
		.core = &_name##_core, \
		};

		#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
		static struct clk_hw_omap _name##_hw = { \
		.hw = { \
		.clk = &_name, \
		}, \
		.clkdm_name = _clkdm_name, \
		};

		#define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \
		_clksel_reg, _clksel_mask, \
		_parent_names, _ops) \
		static struct clk _name; \
		static struct clk_hw_omap _name##_hw = { \
		.hw = { \
		.clk = &_name, \
		}, \
		.clksel = _clksel, \
		.clksel_reg = _clksel_reg, \
		.clksel_mask = _clksel_mask, \
		.clkdm_name = _clkdm_name, \
		}; \
		DEFINE_STRUCT_CLK(_name, _parent_names, _ops);

		#define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \
		_clksel_reg, _clksel_mask, \
		_enable_reg, _enable_bit, \
		_hwops, _parent_names, _ops) \
		static struct clk _name; \
		static struct clk_hw_omap _name##_hw = { \
		.hw = { \
		.clk = &_name, \
		}, \
		.ops = _hwops, \
		.enable_reg = _enable_reg, \
		.enable_bit = _enable_bit, \
		.clksel = _clksel, \
		.clksel_reg = _clksel_reg, \
		.clksel_mask = _clksel_mask, \
		.clkdm_name = _clkdm_name, \
		}; \
		DEFINE_STRUCT_CLK(_name, _parent_names, _ops);

		/* struct clksel_rate.flags possibilities */
		#define RATE_IN_242X (1 << 0)
		#define RATE_IN_243X (1 << 1)
		@@ -127,38 +43,6 @@ struct clockdomain;
		/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
		#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS \| RATE_IN_36XX)


		/**
		* struct clksel_rate - register bitfield values corresponding to clk divisors
		* @val: register bitfield value (shifted to bit 0)
		* @div: clock divisor corresponding to @val
		* @flags: (see "struct clksel_rate.flags possibilities" above)
		*
		* @val should match the value of a read from struct clk.clksel_reg
		* AND'ed with struct clk.clksel_mask, shifted right to bit 0.
		*
		* @div is the divisor that should be applied to the parent clock's rate
		* to produce the current clock's rate.
		*/
		struct clksel_rate {
		u32 val;
		u8 div;
		u16 flags;
		};

		/**
		* struct clksel - available parent clocks, and a pointer to their divisors
		* @parent: struct clk * to a possible parent clock
		* @rates: available divisors for this parent clock
		*
		* A struct clksel is always associated with one or more struct clks
		* and one or more struct clksel_rates.
		*/
		struct clksel {
		struct clk *parent;
		const struct clksel_rate *rates;
		};

		/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
		#define CORE_CLK_SRC_32K 0x0
		#define CORE_CLK_SRC_DPLL 0x1
		@@ -180,105 +64,18 @@ struct clksel {
		#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
		#define OMAP4XXX_EN_DPLL_LOCKED 0x7

		u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
		void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
		void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
		void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
		void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);

		void __init omap2_clk_disable_clkdm_control(void);

		/* clkt_clksel.c public functions */
		u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
		unsigned long target_rate,
		u32 *new_div);
		u8 omap2_clksel_find_parent_index(struct clk_hw *hw);
		unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate);
		long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
		unsigned long *parent_rate);
		int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate);
		int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);

		/* clkt_iclk.c public functions */
		extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
		extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);

		unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);

		void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
		void __iomem **other_reg,
		u8 *other_bit);
		void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
		void __iomem **idlest_reg,
		u8 idlest_bit, u8 idlest_val);
		int omap2_clk_enable_autoidle_all(void);
		int omap2_clk_allow_idle(struct clk *clk);
		int omap2_clk_deny_idle(struct clk *clk);
		int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
		void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
		const char *core_ck_name,
		const char *mpu_ck_name);

		u32 omap2_clk_readl(struct clk_hw_omap clk, void __iomem reg);
		void omap2_clk_writel(u32 val, struct clk_hw_omap clk, void __iomem reg);

		extern u16 cpu_mask;

		/*
		* Clock features setup. Used instead of CPU type checks.
		*/
		struct ti_clk_features {
		u32 flags;
		long fint_min;
		long fint_max;
		long fint_band1_max;
		long fint_band2_min;
		u8 dpll_bypass_vals;
		u8 cm_idlest_val;
		};

		#define TI_CLK_DPLL_HAS_FREQSEL (1 << 0)
		#define TI_CLK_DPLL4_DENY_REPROGRAM (1 << 1)

		extern struct ti_clk_features ti_clk_features;

		extern const struct clkops clkops_omap2_dflt_wait;
		extern const struct clkops clkops_omap2_dflt;

		extern struct clk_functions omap2_clk_functions;

		extern const struct clksel_rate gpt_32k_rates[];
		extern const struct clksel_rate gpt_sys_rates[];
		extern const struct clksel_rate gfx_l3_rates[];
		extern const struct clksel_rate dsp_ick_rates[];

		extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
		extern const struct clk_hw_omap_ops clkhwops_wait;
		extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
		extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
		extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
		extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
		extern const struct clk_hw_omap_ops clkhwops_apll54;
		extern const struct clk_hw_omap_ops clkhwops_apll96;

		/* clksel_rate blocks shared between OMAP44xx and AM33xx */
		extern const struct clksel_rate div_1_0_rates[];
		extern const struct clksel_rate div3_1to4_rates[];
		extern const struct clksel_rate div_1_1_rates[];
		extern const struct clksel_rate div_1_2_rates[];
		extern const struct clksel_rate div_1_3_rates[];
		extern const struct clksel_rate div_1_4_rates[];
		extern const struct clksel_rate div31_1to31_rates[];

		extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
		extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);

		struct regmap;

		int __init omap2_clk_provider_init(struct device_node *np, int index,
		struct regmap syscon, void __iomem mem);
		void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem);
		int __init omap2_clk_setup_ll_ops(void);

		void __init ti_clk_init_features(void);
		#endif

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