Commit 4d154d33 authored by Swati Sharma's avatar Swati Sharma Committed by Jani Nikula
Browse files

drm/i915/display: Extract chv_read_luts() 

For cherryview, add hw read out to create hw blob of gamma
lut values.

Review comments from previous series:
https://patchwork.freedesktop.org/patch/328252



v4: -No need to initialize *blob [Jani]
    -Removed right shifts [Jani]
    -Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally within the
     function [Ville]
    -Renamed function cherryview_get_color_config() to chv_read_luts()
    -Renamed cherryview_get_gamma_config() to chv_read_cgm_gamma_lut()
     [Ville]
v9: -80 character limit [Uma]
    -Made read func para as const [Ville, Uma]
    -Renamed chv_read_cgm_gamma_lut() to chv_read_cgm_gamma_lut()
     [Ville, Uma]

Signed-off-by: default avatarSwati Sharma <swati2.sharma@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1568030503-26747-4-git-send-email-swati2.sharma@intel.com
parent 8efd0698

drivers/gpu/drm/i915/display/intel_color.c

+43 −0
Original line number Diff line number Diff line
@@ -1618,6 +1618,48 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state) 
		crtc_state->base.gamma_lut = i965_read_lut_10p6(crtc_state);

}



static struct drm_property_blob *

chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;

	enum pipe pipe = crtc->pipe;

	struct drm_property_blob *blob;

	struct drm_color_lut *blob_data;

	u32 i, val;



	blob = drm_property_create_blob(&dev_priv->drm,

					sizeof(struct drm_color_lut) * lut_size,

					NULL);

	if (IS_ERR(blob))

		return NULL;



	blob_data = blob->data;



	for (i = 0; i < lut_size; i++) {

		val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));

		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(

							  CGM_PIPE_GAMMA_GREEN_MASK, val), 10);

		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(

							 CGM_PIPE_GAMMA_BLUE_MASK, val), 10);



		val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1));

		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(

							CGM_PIPE_GAMMA_RED_MASK, val), 10);

	}



	return blob;

}



static void chv_read_luts(struct intel_crtc_state *crtc_state)

{

	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)

		crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);

	else

		crtc_state->base.gamma_lut = chv_read_cgm_lut(crtc_state);

}



static struct drm_property_blob *

ilk_read_lut_10(const struct intel_crtc_state *crtc_state)

{
@@ -1717,6 +1759,7 @@ void intel_color_init(struct intel_crtc *crtc) 
			dev_priv->display.color_check = chv_color_check;

			dev_priv->display.color_commit = i9xx_color_commit;

			dev_priv->display.load_luts = chv_load_luts;

			dev_priv->display.read_luts = chv_read_luts;

		} else if (INTEL_GEN(dev_priv) >= 4) {

			dev_priv->display.color_check = i9xx_color_check;

			dev_priv->display.color_commit = i9xx_color_commit;

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -10421,6 +10421,9 @@ enum skl_power_gate { 
#define   CGM_PIPE_MODE_GAMMA	(1 << 2)

#define   CGM_PIPE_MODE_CSC	(1 << 1)

#define   CGM_PIPE_MODE_DEGAMMA	(1 << 0)

#define   CGM_PIPE_GAMMA_RED_MASK   REG_GENMASK(9, 0)

#define   CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16)

#define   CGM_PIPE_GAMMA_BLUE_MASK  REG_GENMASK(9, 0)



#define _CGM_PIPE_B_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x69900)

#define _CGM_PIPE_B_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x69904)

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