Commit 4cdc2ec1 authored by addy ke's avatar addy ke Committed by Ulf Hansson
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mmc: dw_mmc: move rockchip related code to a separate file 



To support HS200 and UHS-1, we need add a big hunk of code,
as shown in the following patches. So a separate file for
rockchip SOCs is suitable.

Signed-off-by: default avatarAddy Ke <addy.ke@rock-chips.com>
Acked-by: default avatarJaehoon Chung <jh80.chung@samsung.com>
Tested-by: default avatarDoug Anderson <dianders@chromium.org>
Reviewed-by: default avatarDoug Anderson <dianders@chromium.org>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent da29fe2b

drivers/mmc/host/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -638,6 +638,15 @@ config MMC_DW_PCI 


	  If unsure, say N.



config MMC_DW_ROCKCHIP

	tristate "Rockchip specific extensions for Synopsys DW Memory Card Interface"

	depends on MMC_DW && ARCH_ROCKCHIP

	select MMC_DW_PLTFM

	help

	  This selects support for Rockchip SoC specific extensions to the

	  Synopsys DesignWare Memory Card Interface driver. Select this option

	  for platforms based on RK3066, RK3188 and RK3288 SoC's.



config MMC_SH_MMCIF

	tristate "SuperH Internal MMCIF support"

	depends on MMC_BLOCK && HAS_DMA

drivers/mmc/host/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ obj-$(CONFIG_MMC_DW_PLTFM) += dw_mmc-pltfm.o 
obj-$(CONFIG_MMC_DW_EXYNOS)	+= dw_mmc-exynos.o

obj-$(CONFIG_MMC_DW_K3)		+= dw_mmc-k3.o

obj-$(CONFIG_MMC_DW_PCI)	+= dw_mmc-pci.o

obj-$(CONFIG_MMC_DW_ROCKCHIP)	+= dw_mmc-rockchip.o

obj-$(CONFIG_MMC_SH_MMCIF)	+= sh_mmcif.o

obj-$(CONFIG_MMC_JZ4740)	+= jz4740_mmc.o

obj-$(CONFIG_MMC_VUB300)	+= vub300.o

drivers/mmc/host/dw_mmc-pltfm.c

+0 −57
Original line number Diff line number Diff line
@@ -26,64 +26,11 @@ 
#include "dw_mmc.h"

#include "dw_mmc-pltfm.h"



#define RK3288_CLKGEN_DIV	2



static void dw_mci_pltfm_prepare_command(struct dw_mci *host, u32 *cmdr)

{

	*cmdr |= SDMMC_CMD_USE_HOLD_REG;

}



static int dw_mci_rk3288_setup_clock(struct dw_mci *host)

{

	host->bus_hz /= RK3288_CLKGEN_DIV;



	return 0;

}



static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)

{

	int ret;

	unsigned int cclkin;

	u32 bus_hz;



	/*

	 * cclkin: source clock of mmc controller.

	 * bus_hz: card interface clock generated by CLKGEN.

	 * bus_hz = cclkin / RK3288_CLKGEN_DIV;

	 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))

	 *

	 * Note: div can only be 0 or 1

	 *       if DDR50 8bit mode(only emmc work in 8bit mode),

	 *       div must be set 1

	 */

	if ((ios->bus_width == MMC_BUS_WIDTH_8) &&

	    (ios->timing == MMC_TIMING_MMC_DDR52))

		cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;

	else

		cclkin = ios->clock * RK3288_CLKGEN_DIV;



	ret = clk_set_rate(host->ciu_clk, cclkin);

	if (ret)

		dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);



	bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;

	if (bus_hz != host->bus_hz) {

		host->bus_hz = bus_hz;

		/* force dw_mci_setup_bus() */

		host->current_speed = 0;

	}

}



static const struct dw_mci_drv_data rk2928_drv_data = {

	.prepare_command	= dw_mci_pltfm_prepare_command,

};



static const struct dw_mci_drv_data rk3288_drv_data = {

	.prepare_command	= dw_mci_pltfm_prepare_command,

	.set_ios	= dw_mci_rk3288_set_ios,

	.setup_clock	= dw_mci_rk3288_setup_clock,

};



static const struct dw_mci_drv_data socfpga_drv_data = {

	.prepare_command	= dw_mci_pltfm_prepare_command,

};
@@ -141,10 +88,6 @@ EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops); 


static const struct of_device_id dw_mci_pltfm_match[] = {

	{ .compatible = "snps,dw-mshc", },

	{ .compatible = "rockchip,rk2928-dw-mshc",

		.data = &rk2928_drv_data },

	{ .compatible = "rockchip,rk3288-dw-mshc",

		.data = &rk3288_drv_data },

	{ .compatible = "altr,socfpga-dw-mshc",

		.data = &socfpga_drv_data },

	{},

drivers/mmc/host/dw_mmc-rockchip.c

0 → 100644
+136 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */



#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/clk.h>

#include <linux/mmc/host.h>

#include <linux/mmc/dw_mmc.h>

#include <linux/of_address.h>



#include "dw_mmc.h"

#include "dw_mmc-pltfm.h"



#define RK3288_CLKGEN_DIV       2



static void dw_mci_rockchip_prepare_command(struct dw_mci *host, u32 *cmdr)

{

	*cmdr |= SDMMC_CMD_USE_HOLD_REG;

}



static int dw_mci_rk3288_setup_clock(struct dw_mci *host)

{

	host->bus_hz /= RK3288_CLKGEN_DIV;



	return 0;

}



static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)

{

	int ret;

	unsigned int cclkin;

	u32 bus_hz;



	/*

	 * cclkin: source clock of mmc controller

	 * bus_hz: card interface clock generated by CLKGEN

	 * bus_hz = cclkin / RK3288_CLKGEN_DIV

	 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))

	 *

	 * Note: div can only be 0 or 1

	 *       if DDR50 8bit mode(only emmc work in 8bit mode),

	 *       div must be set 1

	 */

	if (ios->bus_width == MMC_BUS_WIDTH_8 &&

	    ios->timing == MMC_TIMING_MMC_DDR52)

		cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;

	else

		cclkin = ios->clock * RK3288_CLKGEN_DIV;



	ret = clk_set_rate(host->ciu_clk, cclkin);

	if (ret)

		dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);



	bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;

	if (bus_hz != host->bus_hz) {

		host->bus_hz = bus_hz;

		/* force dw_mci_setup_bus() */

		host->current_speed = 0;

	}

}



static const struct dw_mci_drv_data rk2928_drv_data = {

	.prepare_command        = dw_mci_rockchip_prepare_command,

};



static const struct dw_mci_drv_data rk3288_drv_data = {

	.prepare_command        = dw_mci_rockchip_prepare_command,

	.set_ios		= dw_mci_rk3288_set_ios,

	.setup_clock    = dw_mci_rk3288_setup_clock,

};



static const struct of_device_id dw_mci_rockchip_match[] = {

	{ .compatible = "rockchip,rk2928-dw-mshc",

		.data = &rk2928_drv_data },

	{ .compatible = "rockchip,rk3288-dw-mshc",

		.data = &rk3288_drv_data },

	{},

};

MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);



static int dw_mci_rockchip_probe(struct platform_device *pdev)

{

	const struct dw_mci_drv_data *drv_data;

	const struct of_device_id *match;



	if (!pdev->dev.of_node)

		return -ENODEV;



	match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);

	drv_data = match->data;



	return dw_mci_pltfm_register(pdev, drv_data);

}



#ifdef CONFIG_PM_SLEEP

static int dw_mci_rockchip_suspend(struct device *dev)

{

	struct dw_mci *host = dev_get_drvdata(dev);



	return dw_mci_suspend(host);

}



static int dw_mci_rockchip_resume(struct device *dev)

{

	struct dw_mci *host = dev_get_drvdata(dev);



	return dw_mci_resume(host);

}

#endif /* CONFIG_PM_SLEEP */



static SIMPLE_DEV_PM_OPS(dw_mci_rockchip_pmops,

			 dw_mci_rockchip_suspend,

			 dw_mci_rockchip_resume);



static struct platform_driver dw_mci_rockchip_pltfm_driver = {

	.probe		= dw_mci_rockchip_probe,

	.remove		= __exit_p(dw_mci_pltfm_remove),

	.driver		= {

		.name		= "dwmmc_rockchip",

		.of_match_table	= dw_mci_rockchip_match,

		.pm		= &dw_mci_rockchip_pmops,

	},

};



module_platform_driver(dw_mci_rockchip_pltfm_driver);



MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");

MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");

MODULE_ALIAS("platform:dwmmc-rockchip");

MODULE_LICENSE("GPL v2");

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