Commit 4cc1feeb authored by David S. Miller's avatar David S. Miller
Browse files


Several conflicts, seemingly all over the place.

I used Stephen Rothwell's sample resolutions for many of these, if not
just to double check my own work, so definitely the credit largely
goes to him.

The NFP conflict consisted of a bug fix (moving operations
past the rhashtable operation) while chaning the initial
argument in the function call in the moved code.

The net/dsa/master.c conflict had to do with a bug fix intermixing of
making dsa_master_set_mtu() static with the fixing of the tagging
attribute location.

cls_flower had a conflict because the dup reject fix from Or
overlapped with the addition of port range classifiction.

__set_phy_supported()'s conflict was relatively easy to resolve
because Andrew fixed it in both trees, so it was just a matter
of taking the net-next copy.  Or at least I think it was :-)

Joe Stringer's fix to the handling of netns id 0 in bpf_sk_lookup()
intermixed with changes on how the sdif and caller_net are calculated
in these code paths in net-next.

The remaining BPF conflicts were largely about the addition of the
__bpf_md_ptr stuff in 'net' overlapping with adjustments and additions
to the relevant data structure where the MD pointer macros are used.

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents a60956ed 40e020c1
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What:		/sys/class/net/<iface>/tagging
What:		/sys/class/net/<iface>/dsa/tagging
Date:		August 2018
Date:		August 2018
KernelVersion:	4.20
KernelVersion:	4.20
Contact:	netdev@vger.kernel.org
Contact:	netdev@vger.kernel.org
+60 −3
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@@ -856,7 +856,8 @@
			causing system reset or hang due to sending
			causing system reset or hang due to sending
			INIT from AP to BSP.
			INIT from AP to BSP.


	disable_counter_freezing [HW]
	perf_v4_pmi=	[X86,INTEL]
			Format: <bool>
			Disable Intel PMU counter freezing feature.
			Disable Intel PMU counter freezing feature.
			The feature only exists starting from
			The feature only exists starting from
			Arch Perfmon v4 (Skylake and newer).
			Arch Perfmon v4 (Skylake and newer).
@@ -3504,6 +3505,10 @@
			before loading.
			before loading.
			See Documentation/blockdev/ramdisk.txt.
			See Documentation/blockdev/ramdisk.txt.


	psi=		[KNL] Enable or disable pressure stall information
			tracking.
			Format: <bool>

	psmouse.proto=	[HW,MOUSE] Highest PS2 mouse protocol extension to
	psmouse.proto=	[HW,MOUSE] Highest PS2 mouse protocol extension to
			probe for; one of (bare|imps|exps|lifebook|any).
			probe for; one of (bare|imps|exps|lifebook|any).
	psmouse.rate=	[HW,MOUSE] Set desired mouse report rate, in reports
	psmouse.rate=	[HW,MOUSE] Set desired mouse report rate, in reports
@@ -4194,9 +4199,13 @@


	spectre_v2=	[X86] Control mitigation of Spectre variant 2
	spectre_v2=	[X86] Control mitigation of Spectre variant 2
			(indirect branch speculation) vulnerability.
			(indirect branch speculation) vulnerability.
			The default operation protects the kernel from
			user space attacks.


			on   - unconditionally enable
			on   - unconditionally enable, implies
			off  - unconditionally disable
			       spectre_v2_user=on
			off  - unconditionally disable, implies
			       spectre_v2_user=off
			auto - kernel detects whether your CPU model is
			auto - kernel detects whether your CPU model is
			       vulnerable
			       vulnerable


@@ -4206,6 +4215,12 @@
			CONFIG_RETPOLINE configuration option, and the
			CONFIG_RETPOLINE configuration option, and the
			compiler with which the kernel was built.
			compiler with which the kernel was built.


			Selecting 'on' will also enable the mitigation
			against user space to user space task attacks.

			Selecting 'off' will disable both the kernel and
			the user space protections.

			Specific mitigations can also be selected manually:
			Specific mitigations can also be selected manually:


			retpoline	  - replace indirect branches
			retpoline	  - replace indirect branches
@@ -4215,6 +4230,48 @@
			Not specifying this option is equivalent to
			Not specifying this option is equivalent to
			spectre_v2=auto.
			spectre_v2=auto.


	spectre_v2_user=
			[X86] Control mitigation of Spectre variant 2
		        (indirect branch speculation) vulnerability between
		        user space tasks

			on	- Unconditionally enable mitigations. Is
				  enforced by spectre_v2=on

			off     - Unconditionally disable mitigations. Is
				  enforced by spectre_v2=off

			prctl   - Indirect branch speculation is enabled,
				  but mitigation can be enabled via prctl
				  per thread.  The mitigation control state
				  is inherited on fork.

			prctl,ibpb
				- Like "prctl" above, but only STIBP is
				  controlled per thread. IBPB is issued
				  always when switching between different user
				  space processes.

			seccomp
				- Same as "prctl" above, but all seccomp
				  threads will enable the mitigation unless
				  they explicitly opt out.

			seccomp,ibpb
				- Like "seccomp" above, but only STIBP is
				  controlled per thread. IBPB is issued
				  always when switching between different
				  user space processes.

			auto    - Kernel selects the mitigation depending on
				  the available CPU features and vulnerability.

			Default mitigation:
			If CONFIG_SECCOMP=y then "seccomp", otherwise "prctl"

			Not specifying this option is equivalent to
			spectre_v2_user=auto.

	spec_store_bypass_disable=
	spec_store_bypass_disable=
			[HW] Control Speculative Store Bypass (SSB) Disable mitigation
			[HW] Control Speculative Store Bypass (SSB) Disable mitigation
			(Speculative Store Bypass vulnerability)
			(Speculative Store Bypass vulnerability)
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@@ -57,6 +57,7 @@ stable kernels.
| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |
| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |
| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |
| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |
| ARM            | Cortex-A76      | #1188873        | ARM64_ERRATUM_1188873       |
| ARM            | Cortex-A76      | #1188873        | ARM64_ERRATUM_1188873       |
| ARM            | Cortex-A76      | #1286807        | ARM64_ERRATUM_1286807       |
| ARM            | MMU-500         | #841119,#826419 | N/A                         |
| ARM            | MMU-500         | #841119,#826419 | N/A                         |
|                |                 |                 |                             |
|                |                 |                 |                             |
| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |
| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |
+16 −0
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@@ -168,3 +168,19 @@ a shared clock is forbidden.


Configuration of common clocks, which affect multiple consumer devices can
Configuration of common clocks, which affect multiple consumer devices can
be similarly specified in the clock provider node.
be similarly specified in the clock provider node.

==Protected clocks==

Some platforms or firmwares may not fully expose all the clocks to the OS, such
as in situations where those clks are used by drivers running in ARM secure
execution levels. Such a configuration can be specified in device tree with the
protected-clocks property in the form of a clock specifier list. This property should
only be specified in the node that is providing the clocks being protected:

   clock-controller@a000f000 {
        compatible = "vendor,clk95;
        reg = <0xa000f000 0x1000>
        #clocks-cells = <1>;
        ...
        protected-clocks = <UART3_CLK>, <SPI5_CLK>;
   };
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@@ -12,7 +12,7 @@ The /chosen node should contain a 'linux,sysrq-reset-seq' child node to define
a set of keys.
a set of keys.


Required property:
Required property:
sysrq-reset-seq: array of Linux keycodes, one keycode per cell.
keyset: array of Linux keycodes, one keycode per cell.


Optional property:
Optional property:
timeout-ms: duration keys must be pressed together in milliseconds before
timeout-ms: duration keys must be pressed together in milliseconds before
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