Commit 4cc1178e authored by Dennis Li's avatar Dennis Li Committed by Alex Deucher
Browse files

drm/amdgpu: replace DRM prefix with PCI device info for gfx/mmhub 



Prefix RAS message printing in gfx/mmhub with PCI device info,
which assists the debug in multiple GPU case.

Reviewed-by: default avatarGuchun Chen <guchun.chen@amd.com>
Signed-off-by: default avatarDennis Li <Dennis.Li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f9b93c9b

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

100644 → 100755
+23 −12
Original line number Diff line number Diff line
@@ -732,7 +732,8 @@ static int gfx_v9_4_query_utc_edc_status(struct amdgpu_device *adev, 
		sec_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL,

					  SEC_COUNT);

		if (sec_count) {

			DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,

			dev_info(adev->dev,

				 "Instance[%d]: SubBlock %s, SEC %d\n", i,

				 vml2_walker_mems[i], sec_count);

			err_data->ce_count += sec_count;

		}
@@ -740,7 +741,8 @@ static int gfx_v9_4_query_utc_edc_status(struct amdgpu_device *adev, 
		ded_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL,

					  DED_COUNT);

		if (ded_count) {

			DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,

			dev_info(adev->dev,

				 "Instance[%d]: SubBlock %s, DED %d\n", i,

				 vml2_walker_mems[i], ded_count);

			err_data->ue_count += ded_count;

		}
@@ -752,14 +754,16 @@ static int gfx_v9_4_query_utc_edc_status(struct amdgpu_device *adev, 


		sec_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, SEC_COUNT);

		if (sec_count) {

			DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,

			dev_info(adev->dev,

				 "Instance[%d]: SubBlock %s, SEC %d\n", i,

				 utcl2_router_mems[i], sec_count);

			err_data->ce_count += sec_count;

		}



		ded_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, DED_COUNT);

		if (ded_count) {

			DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,

			dev_info(adev->dev,

				 "Instance[%d]: SubBlock %s, DED %d\n", i,

				 utcl2_router_mems[i], ded_count);

			err_data->ue_count += ded_count;

		}
@@ -772,7 +776,8 @@ static int gfx_v9_4_query_utc_edc_status(struct amdgpu_device *adev, 
		sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL,

					  SEC_COUNT);

		if (sec_count) {

			DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,

			dev_info(adev->dev,

				 "Instance[%d]: SubBlock %s, SEC %d\n", i,

				 atc_l2_cache_2m_mems[i], sec_count);

			err_data->ce_count += sec_count;

		}
@@ -780,7 +785,8 @@ static int gfx_v9_4_query_utc_edc_status(struct amdgpu_device *adev, 
		ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL,

					  DED_COUNT);

		if (ded_count) {

			DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,

			dev_info(adev->dev,

				 "Instance[%d]: SubBlock %s, DED %d\n", i,

				 atc_l2_cache_2m_mems[i], ded_count);

			err_data->ue_count += ded_count;

		}
@@ -793,7 +799,8 @@ static int gfx_v9_4_query_utc_edc_status(struct amdgpu_device *adev, 
		sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL,

					  SEC_COUNT);

		if (sec_count) {

			DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,

			dev_info(adev->dev,

				 "Instance[%d]: SubBlock %s, SEC %d\n", i,

				 atc_l2_cache_4k_mems[i], sec_count);

			err_data->ce_count += sec_count;

		}
@@ -801,7 +808,8 @@ static int gfx_v9_4_query_utc_edc_status(struct amdgpu_device *adev, 
		ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL,

					  DED_COUNT);

		if (ded_count) {

			DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,

			dev_info(adev->dev,

				 "Instance[%d]: SubBlock %s, DED %d\n", i,

				 atc_l2_cache_4k_mems[i], ded_count);

			err_data->ue_count += ded_count;

		}
@@ -816,7 +824,8 @@ static int gfx_v9_4_query_utc_edc_status(struct amdgpu_device *adev, 
	return 0;

}



static int gfx_v9_4_ras_error_count(const struct soc15_reg_entry *reg,

static int gfx_v9_4_ras_error_count(struct amdgpu_device *adev,

				    const struct soc15_reg_entry *reg,

				    uint32_t se_id, uint32_t inst_id,

				    uint32_t value, uint32_t *sec_count,

				    uint32_t *ded_count)
@@ -833,7 +842,8 @@ static int gfx_v9_4_ras_error_count(const struct soc15_reg_entry *reg, 
		sec_cnt = (value & gfx_v9_4_ras_fields[i].sec_count_mask) >>

			  gfx_v9_4_ras_fields[i].sec_count_shift;

		if (sec_cnt) {

			DRM_INFO("GFX SubBlock %s, Instance[%d][%d], SEC %d\n",

			dev_info(adev->dev,

				 "GFX SubBlock %s, Instance[%d][%d], SEC %d\n",

				 gfx_v9_4_ras_fields[i].name, se_id, inst_id,

				 sec_cnt);

			*sec_count += sec_cnt;
@@ -842,7 +852,8 @@ static int gfx_v9_4_ras_error_count(const struct soc15_reg_entry *reg, 
		ded_cnt = (value & gfx_v9_4_ras_fields[i].ded_count_mask) >>

			  gfx_v9_4_ras_fields[i].ded_count_shift;

		if (ded_cnt) {

			DRM_INFO("GFX SubBlock %s, Instance[%d][%d], DED %d\n",

			dev_info(adev->dev,

				 "GFX SubBlock %s, Instance[%d][%d], DED %d\n",

				 gfx_v9_4_ras_fields[i].name, se_id, inst_id,

				 ded_cnt);

			*ded_count += ded_cnt;
@@ -876,7 +887,7 @@ int gfx_v9_4_query_ras_error_count(struct amdgpu_device *adev, 
				reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(

					gfx_v9_4_edc_counter_regs[i]));

				if (reg_value)

					gfx_v9_4_ras_error_count(

					gfx_v9_4_ras_error_count(adev,

						&gfx_v9_4_edc_counter_regs[i],

						j, k, reg_value, &sec_count,

						&ded_count);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

100644 → 100755
+8 −4
Original line number Diff line number Diff line
@@ -690,7 +690,8 @@ static const struct soc15_reg_entry mmhub_v1_0_edc_cnt_regs[] = { 
   { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 0, 0, 0},

};



static int mmhub_v1_0_get_ras_error_count(const struct soc15_reg_entry *reg,

static int mmhub_v1_0_get_ras_error_count(struct amdgpu_device *adev,

	const struct soc15_reg_entry *reg,

	uint32_t value, uint32_t *sec_count, uint32_t *ded_count)

{

	uint32_t i;
@@ -704,7 +705,8 @@ static int mmhub_v1_0_get_ras_error_count(const struct soc15_reg_entry *reg, 
				mmhub_v1_0_ras_fields[i].sec_count_mask) >>

				mmhub_v1_0_ras_fields[i].sec_count_shift;

		if (sec_cnt) {

			DRM_INFO("MMHUB SubBlock %s, SEC %d\n",

			dev_info(adev->dev,

				"MMHUB SubBlock %s, SEC %d\n",

				mmhub_v1_0_ras_fields[i].name,

				sec_cnt);

			*sec_count += sec_cnt;
@@ -714,7 +716,8 @@ static int mmhub_v1_0_get_ras_error_count(const struct soc15_reg_entry *reg, 
				mmhub_v1_0_ras_fields[i].ded_count_mask) >>

				mmhub_v1_0_ras_fields[i].ded_count_shift;

		if (ded_cnt) {

			DRM_INFO("MMHUB SubBlock %s, DED %d\n",

			dev_info(adev->dev,

				"MMHUB SubBlock %s, DED %d\n",

				mmhub_v1_0_ras_fields[i].name,

				ded_cnt);

			*ded_count += ded_cnt;
@@ -739,7 +742,8 @@ static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev, 
		reg_value =

			RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i]));

		if (reg_value)

			mmhub_v1_0_get_ras_error_count(&mmhub_v1_0_edc_cnt_regs[i],

			mmhub_v1_0_get_ras_error_count(adev,

				&mmhub_v1_0_edc_cnt_regs[i],

				reg_value, &sec_count, &ded_count);

	}

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