Commit 4cc0e36d authored by Cédric Le Goater's avatar Cédric Le Goater Committed by Michael Ellerman
Browse files

powerpc/xive: Remove P9 DD1 flag XIVE_IRQ_FLAG_SHIFT_BUG 

This flag was used to support the PHB4 LSIs on P9 DD1 and we have
stopped supporting this CPU when DD2 came out. See skiboot commit:

  https://github.com/open-power/skiboot/commit/0b0d15e3c170



Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
Reviewed-by: default avatarGreg Kurz <groug@kaod.org>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20201210171450.1933725-9-clg@kaod.org
parent 7b3b3de3

arch/powerpc/include/asm/opal-api.h

+1 −1
Original line number Diff line number Diff line
@@ -1091,7 +1091,7 @@ enum { 
	OPAL_XIVE_IRQ_TRIGGER_PAGE	= 0x00000001,

	OPAL_XIVE_IRQ_STORE_EOI		= 0x00000002,

	OPAL_XIVE_IRQ_LSI		= 0x00000004,

	OPAL_XIVE_IRQ_SHIFT_BUG		= 0x00000008,

	OPAL_XIVE_IRQ_SHIFT_BUG		= 0x00000008, /* P9 DD1.0 workaround */

	OPAL_XIVE_IRQ_MASK_VIA_FW	= 0x00000010,

	OPAL_XIVE_IRQ_EOI_VIA_FW	= 0x00000020,

};

arch/powerpc/include/asm/xive.h

+1 −1
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ struct xive_irq_data { 
};

#define XIVE_IRQ_FLAG_STORE_EOI	0x01

#define XIVE_IRQ_FLAG_LSI	0x02

#define XIVE_IRQ_FLAG_SHIFT_BUG	0x04

/* #define XIVE_IRQ_FLAG_SHIFT_BUG	0x04 */ /* P9 DD1.0 workaround */

#define XIVE_IRQ_FLAG_MASK_FW	0x08

#define XIVE_IRQ_FLAG_EOI_FW	0x10

#define XIVE_IRQ_FLAG_H_INT_ESB	0x20

arch/powerpc/kvm/book3s_xive_native.c

+0 −3
Original line number Diff line number Diff line
@@ -37,9 +37,6 @@ static u8 xive_vm_esb_load(struct xive_irq_data *xd, u32 offset) 
	 * ordering.

	 */



	if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)

		offset |= offset << 4;



	val = in_be64(xd->eoi_mmio + offset);

	return (u8)val;

}

arch/powerpc/kvm/book3s_xive_template.c

+0 −3
Original line number Diff line number Diff line
@@ -61,9 +61,6 @@ static u8 GLUE(X_PFX,esb_load)(struct xive_irq_data *xd, u32 offset) 
	if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI)

		offset |= XIVE_ESB_LD_ST_MO;



	if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)

		offset |= offset << 4;



	val =__x_readq(__x_eoi_page(xd) + offset);

#ifdef __LITTLE_ENDIAN__

	val >>= 64-8;

arch/powerpc/sysdev/xive/common.c

+0 −9
Original line number Diff line number Diff line
@@ -200,10 +200,6 @@ static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset) 
	if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI)

		offset |= XIVE_ESB_LD_ST_MO;



	/* Handle HW errata */

	if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)

		offset |= offset << 4;



	if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)

		val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);

	else
@@ -214,10 +210,6 @@ static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset) 


static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data)

{

	/* Handle HW errata */

	if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)

		offset |= offset << 4;



	if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)

		xive_ops->esb_rw(xd->hw_irq, offset, data, 1);

	else
@@ -1312,7 +1304,6 @@ static const struct { 
} xive_irq_flags[] = {

	{ XIVE_IRQ_FLAG_STORE_EOI, "STORE_EOI" },

	{ XIVE_IRQ_FLAG_LSI,       "LSI"       },

	{ XIVE_IRQ_FLAG_SHIFT_BUG, "SHIFT_BUG" },

	{ XIVE_IRQ_FLAG_MASK_FW,   "MASK_FW"   },

	{ XIVE_IRQ_FLAG_EOI_FW,    "EOI_FW"    },

	{ XIVE_IRQ_FLAG_H_INT_ESB, "H_INT_ESB" },

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