clk: renesas: r7s9210: Move table update to separate function (4cb1480f) · Commits · 戴 / test

drivers/clk/renesas/r7s9210-cpg-mssr.c

+50 −45

Original line number	Diff line number	Diff line
		@@ -97,42 +97,16 @@ static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = {

		};

		struct clk * __init rza2_cpg_clk_register(struct device *dev,
		const struct cpg_core_clk core, const struct cpg_mssr_info info,
		struct clk *clks, void __iomem base,
		struct raw_notifier_head *notifiers)
		/* The clock dividers in the table vary based on DT and register settings */
		static void __init r7s9210_update_clk_table(struct clk *extal_clk,
		void __iomem *base)
		{
		struct clk *parent;
		unsigned int mult = 1;
		unsigned int div = 1;
		int i;
		u16 frqcr;
		u8 index;
		int i;

		parent = clks[core->parent];
		if (IS_ERR(parent))
		return ERR_CAST(parent);

		switch (core->id) {
		case CLK_MAIN:
		break;

		case CLK_PLL:
		if (cpg_mode)
		mult = 44; /* Divider 1 is 1/2 */
		else
		mult = 88; /* Divider 1 is 1 */
		break;

		default:
		return ERR_PTR(-EINVAL);
		}

		/* Adjust the dividers based on the current FRQCR setting */
		if (core->id == CLK_MAIN) {

		/* If EXTAL is above 12MHz, then we know it is Mode 1 */
		if (clk_get_rate(parent) > 12000000)
		if (clk_get_rate(extal_clk) > 12000000)
		cpg_mode = 1;

		frqcr = clk_readl(base + CPG_FRQCR) & 0xFFF;
		@@ -171,6 +145,37 @@ struct clk * __init rza2_cpg_clk_register(struct device *dev,
		}
		}

		struct clk * __init rza2_cpg_clk_register(struct device *dev,
		const struct cpg_core_clk core, const struct cpg_mssr_info info,
		struct clk *clks, void __iomem base,
		struct raw_notifier_head *notifiers)
		{
		struct clk *parent;
		unsigned int mult = 1;
		unsigned int div = 1;

		parent = clks[core->parent];
		if (IS_ERR(parent))
		return ERR_CAST(parent);

		switch (core->id) {
		case CLK_MAIN:
		break;

		case CLK_PLL:
		if (cpg_mode)
		mult = 44; /* Divider 1 is 1/2 */
		else
		mult = 88; /* Divider 1 is 1 */
		break;

		default:
		return ERR_PTR(-EINVAL);
		}

		if (core->id == CLK_MAIN)
		r7s9210_update_clk_table(parent, base);

		return clk_register_fixed_factor(NULL, core->name,
		__clk_get_name(parent), 0, mult, div);
		}

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