Commit 4c85f628 authored Aug 03, 2020 by Paul Kocialkowski Committed by Mauro Carvalho Chehab Sep 01, 2020

media: ov5640: Correct Bit Div register in clock tree diagram

Although the code is correct and doing the right thing, the clock diagram
showed the wrong register for the bit divider, which had me doubting the
understanding of the tree. Fix this to avoid doubts in the future.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Fixes: aa288248 ("media: ov5640: Adjust the clock based on the expected rate")
Acked-by: Jacopo Mondi <jacopo@jmondi.org>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

parent 9eb88a81

drivers/media/i2c/ov5640.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -751,7 +751,7 @@ static int ov5640_mod_reg(struct ov5640_dev *sensor, u16 reg,
		* +->\| PLL Root Div \| - reg 0x3037, bit 4
		* +-+------------+
		* \| +---------+
		* +->\| Bit Div \| - reg 0x3035, bits 0-3
		* +->\| Bit Div \| - reg 0x3034, bits 0-3
		* +-+-------+
		* \| +-------------+
		* +->\| SCLK Div \| - reg 0x3108, bits 0-1