ARM: shmobile: Common shmobile_scu_base in headsmp-scu.S (4c822845) · Commits · 戴 / test

arch/arm/mach-shmobile/Makefile

+2 −2

Original line number	Diff line number	Diff line
		@@ -16,8 +16,8 @@ obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o
		smp-y := platsmp.o headsmp.o
		smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o
		smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o
		smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o
		smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o
		smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o
		smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o

		# IRQ objects
		obj-$(CONFIG_ARCH_SH7372) += entry-intc.o

arch/arm/mach-shmobile/headsmp-scu.S

+7 −1

Original line number	Diff line number	Diff line
		@@ -39,7 +39,8 @@ ENTRY(shmobile_secondary_vector_scu)
		mrc p15, 0, r0, c0, c0, 5 @ read MIPDR
		and r0, r0, #3 @ mask out cpu ID
		lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits
		mov r1, #0xf0000000 @ SCU base address
		ldr r1, =shmobile_scu_base
		ldr r1, [r1] @ SCU base address
		ldr r2, [r1, #8] @ SCU Power Status Register
		mov r3, #3
		bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode)
		@@ -48,3 +49,8 @@ ENTRY(shmobile_secondary_vector_scu)
		ldr pc, 1f
		1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
		ENDPROC(shmobile_secondary_vector_scu)

		.text
		.globl shmobile_scu_base
		shmobile_scu_base:
		.space 4

arch/arm/mach-shmobile/headsmp-sh73a0.S

deleted100644 → 0

+0 −50

Original line number	Diff line number	Diff line
		/*
		* SMP support for SoC sh73a0
		*
		* Copyright (C) 2012 Bastian Hecht
		*
		* This program is free software; you can redistribute it and/or
		* modify it under the terms of the GNU General Public License as
		* published by the Free Software Foundation; either version 2 of
		* the License, or (at your option) any later version.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
		* GNU General Public License for more details.
		*
		* You should have received a copy of the GNU General Public License
		* along with this program; if not, write to the Free Software
		* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
		* MA 02111-1307 USA
		*/

		#include <linux/linkage.h>
		#include <linux/init.h>
		#include <asm/memory.h>

		__CPUINIT
		/*
		* Reset vector for secondary CPUs.
		*
		* First we turn on L1 cache coherency for our CPU. Then we jump to
		* shmobile_invalidate_start that invalidates the cache and hands over control
		* to the common ARM startup code.
		* This function will be mapped to address 0 by the SBAR register.
		* A normal branch is out of range here so we need a long jump. We jump to
		* the physical address as the MMU is still turned off.
		*/
		.align 12
		ENTRY(sh73a0_secondary_vector)
		mrc p15, 0, r0, c0, c0, 5 @ read MIPDR
		and r0, r0, #3 @ mask out cpu ID
		lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits
		mov r1, #0xf0000000 @ SCU base address
		ldr r2, [r1, #8] @ SCU Power Status Register
		mov r3, #3
		bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode)
		str r2, [r1, #8] @ write back

		ldr pc, 1f
		1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
		ENDPROC(sh73a0_secondary_vector)

arch/arm/mach-shmobile/include/mach/common.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -95,6 +95,7 @@ extern int shmobile_cpu_is_dead(unsigned int cpu);
		static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; }
		#endif

		extern void __iomem *shmobile_scu_base;
		extern void shmobile_smp_init_cpus(unsigned int ncores);

		static inline void __init shmobile_init_late(void)

arch/arm/mach-shmobile/smp-emev2.c

+0 −2

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		@@ -32,8 +32,6 @@

		#define EMEV2_SCU_BASE 0x1e000000

		static void __iomem *shmobile_scu_base;

		static DEFINE_SPINLOCK(scu_lock);

		static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)

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