Commit 4c631826 authored by Yongqiang Sun's avatar Yongqiang Sun Committed by Alex Deucher
Browse files

drm/amd/display: Not check wm and clk change flag in optimized bandwidth. 



[Why]
System isn't able to enter S0i3 due to not send display count 0 to smu.
When dpms off, clk changed flag is cleared alreay, and it is checked
when doing optimized bandwidth, and update clocks is bypassed due to the
flag is unset.

[How]
Remove check flag incide the function since watermark values and clocks
values are checked during update to determine whether to perform it, no
need to check it again outside the function.

Signed-off-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cc493508

drivers/gpu/drm/amd/display/dc/core/dc.c

+4 −0
Original line number Diff line number Diff line
@@ -1378,6 +1378,10 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) 
		}



	dc->hwss.optimize_bandwidth(dc, context);



	dc->clk_optimized_required = false;

	dc->wm_optimized_required = false;



	return true;

}

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+9 −19
Original line number Diff line number Diff line
@@ -2717,30 +2717,20 @@ void dcn10_optimize_bandwidth( 
		hws->funcs.verify_allow_pstate_change_high(dc);



	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {

		if (context->stream_count == 0) {

		if (context->stream_count == 0)

			context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;



		dc->clk_mgr->funcs->update_clocks(

				dc->clk_mgr,

				context,

				true);

		} else if (dc->clk_optimized_required || IS_DIAG_DC(dc->ctx->dce_environment)) {

			dc->clk_mgr->funcs->update_clocks(

								dc->clk_mgr,

								context,

								true);

		}

	}



	if (dc->wm_optimized_required || IS_DIAG_DC(dc->ctx->dce_environment)) {

	hubbub->funcs->program_watermarks(hubbub,

			&context->bw_ctx.bw.dcn.watermarks,

			dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,

			true);

	}



	dc->clk_optimized_required = false;

	dc->wm_optimized_required = false;

	dcn10_stereo_hw_frame_pack_wa(dc, context);



	if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+10 −16
Original line number Diff line number Diff line
@@ -1660,22 +1660,16 @@ void dcn20_optimize_bandwidth( 
{

	struct hubbub *hubbub = dc->res_pool->hubbub;



	if (dc->wm_optimized_required || IS_DIAG_DC(dc->ctx->dce_environment)) {

	/* program dchubbub watermarks */

	hubbub->funcs->program_watermarks(hubbub,

					&context->bw_ctx.bw.dcn.watermarks,

					dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,

					true);

		dc->wm_optimized_required = false;

	}



	if (dc->clk_optimized_required || IS_DIAG_DC(dc->ctx->dce_environment)) {

	dc->clk_mgr->funcs->update_clocks(

			dc->clk_mgr,

			context,

			true);

		dc->clk_optimized_required = false;

	}

}



bool dcn20_update_bandwidth(

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