drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs (4c614831) · Commits · 戴 / test

drivers/gpu/drm/i915/i915_reg.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -4570,6 +4570,7 @@ enum {
		* of the infoframe structure specified by CEA-861. */
		#define VIDEO_DIP_DATA_SIZE 32
		#define VIDEO_DIP_VSC_DATA_SIZE 36
		#define VIDEO_DIP_PPS_DATA_SIZE 132
		#define VIDEO_DIP_CTL _MMIO(0x61170)
		/* Pre HSW: */
		#define VIDEO_DIP_ENABLE (1 << 31)

drivers/gpu/drm/i915/intel_hdmi.c

+19 −2

Original line number	Diff line number	Diff line
		@@ -115,6 +115,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
		switch (type) {
		case DP_SDP_VSC:
		return VIDEO_DIP_ENABLE_VSC_HSW;
		case DP_SDP_PPS:
		return VDIP_ENABLE_PPS;
		case HDMI_INFOFRAME_TYPE_AVI:
		return VIDEO_DIP_ENABLE_AVI_HSW;
		case HDMI_INFOFRAME_TYPE_SPD:
		@@ -136,6 +138,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
		switch (type) {
		case DP_SDP_VSC:
		return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
		case DP_SDP_PPS:
		return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
		case HDMI_INFOFRAME_TYPE_AVI:
		return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
		case HDMI_INFOFRAME_TYPE_SPD:
		@@ -148,6 +152,18 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
		}
		}

		static int hsw_dip_data_size(unsigned int type)
		{
		switch (type) {
		case DP_SDP_VSC:
		return VIDEO_DIP_VSC_DATA_SIZE;
		case DP_SDP_PPS:
		return VIDEO_DIP_PPS_DATA_SIZE;
		default:
		return VIDEO_DIP_DATA_SIZE;
		}
		}

		static void g4x_write_infoframe(struct intel_encoder *encoder,
		const struct intel_crtc_state *crtc_state,
		unsigned int type,
		@@ -382,11 +398,12 @@ static void hsw_write_infoframe(struct intel_encoder *encoder,
		struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
		enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
		i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
		int data_size = type == DP_SDP_VSC ?
		VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
		int data_size;
		int i;
		u32 val = I915_READ(ctl_reg);

		data_size = hsw_dip_data_size(type);

		val &= ~hsw_infoframe_enable(type);
		I915_WRITE(ctl_reg, val);

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