Merge branch 'clk-mediatek' into clk-next

- compatible: Should be one of:

	- "mediatek,mt2701-apmixedsys"

	- "mediatek,mt2712-apmixedsys", "syscon"

	- "mediatek,mt6797-apmixedsys"

	- "mediatek,mt7622-apmixedsys"

	- "mediatek,mt8135-apmixedsys"

	- "mediatek,mt8173-apmixedsys"

- #clock-cells: Must be 1

MediaTek AUDSYS controller

============================

The MediaTek AUDSYS controller provides various clocks to the system.

Required Properties:

- compatible: Should be one of:

	- "mediatek,mt7622-audsys", "syscon"

- #clock-cells: Must be 1

The AUDSYS controller uses the common clk binding from

Documentation/devicetree/bindings/clock/clock-bindings.txt

The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

audsys: audsys@11220000 {

	compatible = "mediatek,mt7622-audsys", "syscon";

	reg = <0 0x11220000 0 0x1000>;

	#clock-cells = <1>;

};

- compatible: Should be:

	- "mediatek,mt2701-bdpsys", "syscon"

	- "mediatek,mt2712-bdpsys", "syscon"

- #clock-cells: Must be 1

The bdpsys controller uses the common clk binding from

- compatible: Should be:

	- "mediatek,mt2701-ethsys", "syscon"

	- "mediatek,mt7622-ethsys", "syscon"

- #clock-cells: Must be 1

The ethsys controller uses the common clk binding from

- compatible: Should be:

	- "mediatek,mt2701-hifsys", "syscon"

	- "mediatek,mt7622-hifsys", "syscon"

- #clock-cells: Must be 1

The hifsys controller uses the common clk binding from