drm/amdgpu: add RAS support for the gfx block of Arcturus (4c461d89) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -120,6 +120,7 @@ amdgpu-y += \
		amdgpu_rlc.o \
		gfx_v8_0.o \
		gfx_v9_0.o \
		gfx_v9_4.o \
		gfx_v10_0.o

		# add async DMA block

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+25 −1

Original line number	Diff line number	Diff line
		@@ -48,6 +48,8 @@

		#include "amdgpu_ras.h"

		#include "gfx_v9_4.h"

		#define GFX9_NUM_GFX_RINGS 1
		#define GFX9_MEC_HPD_SIZE 4096
		#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
		@@ -1950,6 +1952,17 @@ static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
		.query_ras_error_count = &gfx_v9_0_query_ras_error_count
		};

		static const struct amdgpu_gfx_funcs gfx_v9_4_gfx_funcs = {
		.get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
		.select_se_sh = &gfx_v9_0_select_se_sh,
		.read_wave_data = &gfx_v9_0_read_wave_data,
		.read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
		.read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
		.select_me_pipe_q = &gfx_v9_0_select_me_pipe_q,
		.ras_error_inject = &gfx_v9_4_ras_error_inject,
		.query_ras_error_count = &gfx_v9_4_query_ras_error_count
		};

		static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
		{
		u32 gb_addr_config;
		@@ -2001,6 +2014,7 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
		gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
		break;
		case CHIP_ARCTURUS:
		adev->gfx.funcs = &gfx_v9_4_gfx_funcs;
		adev->gfx.config.max_hw_contexts = 8;
		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
		@@ -4265,7 +4279,17 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
		goto fail;
		}

		switch (adev->asic_type)
		{
		case CHIP_VEGA20:
		gfx_v9_0_clear_ras_edc_counter(adev);
		break;
		case CHIP_ARCTURUS:
		gfx_v9_4_clear_ras_edc_counter(adev);
		break;
		default:
		break;
		}

		fail:
		amdgpu_ib_free(adev, &ib, NULL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

0 → 100644

+978 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.h

0 → 100644

+35 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright 2020 Advanced Micro Devices, Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*
		*/

		#ifndef __GFX_V9_4_H__
		#define __GFX_V9_4_H__

		void gfx_v9_4_clear_ras_edc_counter(struct amdgpu_device *adev);

		int gfx_v9_4_query_ras_error_count(struct amdgpu_device *adev,
		void *ras_error_status);

		int gfx_v9_4_ras_error_inject(struct amdgpu_device *adev,
		void *inject_if);

		#endif /* __GFX_V9_4_H__ */

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