Commit 4c387984 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

ARM: dts: omap5: Add l4 interconnect hierarchy and ti-sysc data 



Similar to commit 8f42cb7f ("ARM: dts: omap4: Add l4 interconnect
hierarchy and ti-sysc data"), let's add proper interconnect hierarchy
for l4 interconnect instances with the related ti-sysc interconnect
module data as in Documentation/devicetree/bindings/bus/ti-sysc.txt.

Using ti-sysc driver binding allows us to start dropping legacy platform
data in arch/arm/mach-omap2/omap*hwmod*data.c files later on in favor of
ti-sysc dts data.

This data is generated based on platform data from a booted system
and the interconnect acces protection registers for ranges. To avoid
regressions, we initially validate the device tree provided data
against the existing platform data on boot.

Cc: devicetree@vger.kernel.org
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 10aee7ae

arch/arm/boot/dts/omap5-l4.dtsi

0 → 100644
+2462 −0

File added.

Preview size limit exceeded, changes collapsed.

arch/arm/boot/dts/omap5.dtsi

+6 −682
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
 * Based on "omap4.dtsi"

 */



#include <dt-bindings/bus/ti-sysc.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/pinctrl/omap.h>
@@ -151,178 +152,13 @@ 
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;



		l4_cfg: l4@4a000000 {

			compatible = "ti,omap5-l4-cfg", "simple-bus";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0 0x4a000000 0x22a000>;



			scm_core: scm@2000 {

				compatible = "ti,omap5-scm-core", "simple-bus";

				reg = <0x2000 0x1000>;

				#address-cells = <1>;

				#size-cells = <1>;

				ranges = <0 0x2000 0x800>;



				scm_conf: scm_conf@0 {

					compatible = "syscon";

					reg = <0x0 0x800>;

					#address-cells = <1>;

					#size-cells = <1>;

				};

			};



			scm_padconf_core: scm@2800 {

				compatible = "ti,omap5-scm-padconf-core",

					     "simple-bus";

				#address-cells = <1>;

				#size-cells = <1>;

				ranges = <0 0x2800 0x800>;



				omap5_pmx_core: pinmux@40 {

					compatible = "ti,omap5-padconf",

						     "pinctrl-single";

					reg = <0x40 0x01b6>;

					#address-cells = <1>;

					#size-cells = <0>;

					#pinctrl-cells = <1>;

					#interrupt-cells = <1>;

					interrupt-controller;

					pinctrl-single,register-width = <16>;

					pinctrl-single,function-mask = <0x7fff>;

				};



				omap5_padconf_global: omap5_padconf_global@5a0 {

					compatible = "syscon",

						     "simple-bus";

					reg = <0x5a0 0xec>;

					#address-cells = <1>;

					#size-cells = <1>;

					ranges = <0 0x5a0 0xec>;



					pbias_regulator: pbias_regulator@60 {

						compatible = "ti,pbias-omap5", "ti,pbias-omap";

						reg = <0x60 0x4>;

						syscon = <&omap5_padconf_global>;

						pbias_mmc_reg: pbias_mmc_omap5 {

							regulator-name = "pbias_mmc_omap5";

							regulator-min-microvolt = <1800000>;

							regulator-max-microvolt = <3300000>;

						};

					};

				};

			};



			cm_core_aon: cm_core_aon@4000 {

				compatible = "ti,omap5-cm-core-aon",

					     "simple-bus";

				reg = <0x4000 0x2000>;

				#address-cells = <1>;

				#size-cells = <1>;

				ranges = <0 0x4000 0x2000>;



				cm_core_aon_clocks: clocks {

					#address-cells = <1>;

					#size-cells = <0>;

				};



				cm_core_aon_clockdomains: clockdomains {

				};

		l4_wkup: interconnect@4ae00000 {

		};



			cm_core: cm_core@8000 {

				compatible = "ti,omap5-cm-core", "simple-bus";

				reg = <0x8000 0x3000>;

				#address-cells = <1>;

				#size-cells = <1>;

				ranges = <0 0x8000 0x3000>;



				cm_core_clocks: clocks {

					#address-cells = <1>;

					#size-cells = <0>;

		l4_cfg: interconnect@4a000000 {

		};



				cm_core_clockdomains: clockdomains {

				};

			};

		};



		l4_wkup: l4@4ae00000 {

			compatible = "ti,omap5-l4-wkup", "simple-bus";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0 0x4ae00000 0x2b000>;



			counter32k: counter@4000 {

				compatible = "ti,omap-counter32k";

				reg = <0x4000 0x40>;

				ti,hwmods = "counter_32k";

			};



			prm: prm@6000 {

				compatible = "ti,omap5-prm", "simple-bus";

				reg = <0x6000 0x3000>;

				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

				#address-cells = <1>;

				#size-cells = <1>;

				ranges = <0 0x6000 0x3000>;



				prm_clocks: clocks {

					#address-cells = <1>;

					#size-cells = <0>;

				};



				prm_clockdomains: clockdomains {

				};

			};



			scrm: scrm@a000 {

				compatible = "ti,omap5-scrm";

				reg = <0xa000 0x2000>;



				scrm_clocks: clocks {

					#address-cells = <1>;

					#size-cells = <0>;

				};



				scrm_clockdomains: clockdomains {

				};

			};



			omap5_pmx_wkup: pinmux@c840 {

				compatible = "ti,omap5-padconf",

					     "pinctrl-single";

				reg = <0xc840 0x003c>;

				#address-cells = <1>;

				#size-cells = <0>;

				#pinctrl-cells = <1>;

				#interrupt-cells = <1>;

				interrupt-controller;

				pinctrl-single,register-width = <16>;

				pinctrl-single,function-mask = <0x7fff>;

			};



			omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@cda0 {

				compatible = "ti,omap5-scm-wkup-pad-conf",

					     "simple-bus";

				reg = <0xcda0 0x60>;

				#address-cells = <1>;

				#size-cells = <1>;

				ranges = <0 0xcda0 0x60>;



				scm_wkup_pad_conf: scm_conf@0 {

					compatible = "syscon", "simple-bus";

					reg = <0x0 0x60>;

					#address-cells = <1>;

					#size-cells = <1>;

					ranges = <0 0x0 0x60>;



					scm_wkup_pad_conf_clocks: clocks@0 {

						#address-cells = <1>;

						#size-cells = <0>;

					};

				};

			};

		l4_per: interconnect@48000000 {

		};



		ocmcram: ocmcram@40300000 {
@@ -330,108 +166,6 @@ 
			reg = <0x40300000 0x20000>; /* 128k */

		};



		sdma: dma-controller@4a056000 {

			compatible = "ti,omap4430-sdma";

			reg = <0x4a056000 0x1000>;

			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;

			#dma-cells = <1>;

			dma-channels = <32>;

			dma-requests = <127>;

			ti,hwmods = "dma_system";

		};



		gpio1: gpio@4ae10000 {

			compatible = "ti,omap4-gpio";

			reg = <0x4ae10000 0x200>;

			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "gpio1";

			ti,gpio-always-on;

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpio2: gpio@48055000 {

			compatible = "ti,omap4-gpio";

			reg = <0x48055000 0x200>;

			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "gpio2";

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpio3: gpio@48057000 {

			compatible = "ti,omap4-gpio";

			reg = <0x48057000 0x200>;

			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "gpio3";

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpio4: gpio@48059000 {

			compatible = "ti,omap4-gpio";

			reg = <0x48059000 0x200>;

			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "gpio4";

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpio5: gpio@4805b000 {

			compatible = "ti,omap4-gpio";

			reg = <0x4805b000 0x200>;

			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "gpio5";

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpio6: gpio@4805d000 {

			compatible = "ti,omap4-gpio";

			reg = <0x4805d000 0x200>;

			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "gpio6";

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpio7: gpio@48051000 {

			compatible = "ti,omap4-gpio";

			reg = <0x48051000 0x200>;

			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "gpio7";

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpio8: gpio@48053000 {

			compatible = "ti,omap4-gpio";

			reg = <0x48053000 0x200>;

			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "gpio8";

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpmc: gpmc@50000000 {

			compatible = "ti,omap4430-gpmc";

			reg = <0x50000000 0x1000>;
@@ -451,217 +185,6 @@ 
			#gpio-cells = <2>;

		};



		i2c1: i2c@48070000 {

			compatible = "ti,omap4-i2c";

			reg = <0x48070000 0x100>;

			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			ti,hwmods = "i2c1";

		};



		i2c2: i2c@48072000 {

			compatible = "ti,omap4-i2c";

			reg = <0x48072000 0x100>;

			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			ti,hwmods = "i2c2";

		};



		i2c3: i2c@48060000 {

			compatible = "ti,omap4-i2c";

			reg = <0x48060000 0x100>;

			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			ti,hwmods = "i2c3";

		};



		i2c4: i2c@4807a000 {

			compatible = "ti,omap4-i2c";

			reg = <0x4807a000 0x100>;

			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			ti,hwmods = "i2c4";

		};



		i2c5: i2c@4807c000 {

			compatible = "ti,omap4-i2c";

			reg = <0x4807c000 0x100>;

			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			ti,hwmods = "i2c5";

		};



		hwspinlock: spinlock@4a0f6000 {

			compatible = "ti,omap4-hwspinlock";

			reg = <0x4a0f6000 0x1000>;

			ti,hwmods = "spinlock";

			#hwlock-cells = <1>;

		};



		mcspi1: spi@48098000 {

			compatible = "ti,omap4-mcspi";

			reg = <0x48098000 0x200>;

			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			ti,hwmods = "mcspi1";

			ti,spi-num-cs = <4>;

			dmas = <&sdma 35>,

			       <&sdma 36>,

			       <&sdma 37>,

			       <&sdma 38>,

			       <&sdma 39>,

			       <&sdma 40>,

			       <&sdma 41>,

			       <&sdma 42>;

			dma-names = "tx0", "rx0", "tx1", "rx1",

				    "tx2", "rx2", "tx3", "rx3";

		};



		mcspi2: spi@4809a000 {

			compatible = "ti,omap4-mcspi";

			reg = <0x4809a000 0x200>;

			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			ti,hwmods = "mcspi2";

			ti,spi-num-cs = <2>;

			dmas = <&sdma 43>,

			       <&sdma 44>,

			       <&sdma 45>,

			       <&sdma 46>;

			dma-names = "tx0", "rx0", "tx1", "rx1";

		};



		mcspi3: spi@480b8000 {

			compatible = "ti,omap4-mcspi";

			reg = <0x480b8000 0x200>;

			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			ti,hwmods = "mcspi3";

			ti,spi-num-cs = <2>;

			dmas = <&sdma 15>, <&sdma 16>;

			dma-names = "tx0", "rx0";

		};



		mcspi4: spi@480ba000 {

			compatible = "ti,omap4-mcspi";

			reg = <0x480ba000 0x200>;

			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			ti,hwmods = "mcspi4";

			ti,spi-num-cs = <1>;

			dmas = <&sdma 70>, <&sdma 71>;

			dma-names = "tx0", "rx0";

		};



		uart1: serial@4806a000 {

			compatible = "ti,omap4-uart";

			reg = <0x4806a000 0x100>;

			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "uart1";

			clock-frequency = <48000000>;

		};



		uart2: serial@4806c000 {

			compatible = "ti,omap4-uart";

			reg = <0x4806c000 0x100>;

			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "uart2";

			clock-frequency = <48000000>;

		};



		uart3: serial@48020000 {

			compatible = "ti,omap4-uart";

			reg = <0x48020000 0x100>;

			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "uart3";

			clock-frequency = <48000000>;

		};



		uart4: serial@4806e000 {

			compatible = "ti,omap4-uart";

			reg = <0x4806e000 0x100>;

			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "uart4";

			clock-frequency = <48000000>;

		};



		uart5: serial@48066000 {

			compatible = "ti,omap4-uart";

			reg = <0x48066000 0x100>;

			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "uart5";

			clock-frequency = <48000000>;

		};



		uart6: serial@48068000 {

			compatible = "ti,omap4-uart";

			reg = <0x48068000 0x100>;

			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "uart6";

			clock-frequency = <48000000>;

		};



		mmc1: mmc@4809c000 {

			compatible = "ti,omap4-hsmmc";

			reg = <0x4809c000 0x400>;

			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "mmc1";

			ti,dual-volt;

			ti,needs-special-reset;

			dmas = <&sdma 61>, <&sdma 62>;

			dma-names = "tx", "rx";

			pbias-supply = <&pbias_mmc_reg>;

		};



		mmc2: mmc@480b4000 {

			compatible = "ti,omap4-hsmmc";

			reg = <0x480b4000 0x400>;

			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "mmc2";

			ti,needs-special-reset;

			dmas = <&sdma 47>, <&sdma 48>;

			dma-names = "tx", "rx";

		};



		mmc3: mmc@480ad000 {

			compatible = "ti,omap4-hsmmc";

			reg = <0x480ad000 0x400>;

			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "mmc3";

			ti,needs-special-reset;

			dmas = <&sdma 77>, <&sdma 78>;

			dma-names = "tx", "rx";

		};



		mmc4: mmc@480d1000 {

			compatible = "ti,omap4-hsmmc";

			reg = <0x480d1000 0x400>;

			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "mmc4";

			ti,needs-special-reset;

			dmas = <&sdma 57>, <&sdma 58>;

			dma-names = "tx", "rx";

		};



		mmc5: mmc@480d5000 {

			compatible = "ti,omap4-hsmmc";

			reg = <0x480d5000 0x400>;

			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "mmc5";

			ti,needs-special-reset;

			dmas = <&sdma 59>, <&sdma 60>;

			dma-names = "tx", "rx";

		};



		mmu_dsp: mmu@4a066000 {

			compatible = "ti,omap4-iommu";

			reg = <0x4a066000 0x100>;
@@ -679,12 +202,6 @@ 
			ti,iommu-bus-err-back;

		};



		keypad: keypad@4ae1c000 {

			compatible = "ti,omap4-keypad";

			reg = <0x4ae1c000 0x400>;

			ti,hwmods = "kbd";

		};



		mcpdm: mcpdm@40132000 {

			compatible = "ti,omap4-mcpdm";

			reg = <0x40132000 0x7f>, /* MPU private access */
@@ -755,55 +272,6 @@ 
			status = "disabled";

		};



		mailbox: mailbox@4a0f4000 {

			compatible = "ti,omap4-mailbox";

			reg = <0x4a0f4000 0x200>;

			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "mailbox";

			#mbox-cells = <1>;

			ti,mbox-num-users = <3>;

			ti,mbox-num-fifos = <8>;

			mbox_ipu: mbox_ipu {

				ti,mbox-tx = <0 0 0>;

				ti,mbox-rx = <1 0 0>;

			};

			mbox_dsp: mbox_dsp {

				ti,mbox-tx = <3 0 0>;

				ti,mbox-rx = <2 0 0>;

			};

		};



		timer1: timer@4ae18000 {

			compatible = "ti,omap5430-timer";

			reg = <0x4ae18000 0x80>;

			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "timer1";

			ti,timer-alwon;

			clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;

			clock-names = "fck";

		};



		timer2: timer@48032000 {

			compatible = "ti,omap5430-timer";

			reg = <0x48032000 0x80>;

			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "timer2";

		};



		timer3: timer@48034000 {

			compatible = "ti,omap5430-timer";

			reg = <0x48034000 0x80>;

			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "timer3";

		};



		timer4: timer@48036000 {

			compatible = "ti,omap5430-timer";

			reg = <0x48036000 0x80>;

			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "timer4";

		};



		timer5: timer@40138000 {

			compatible = "ti,omap5430-timer";

			reg = <0x40138000 0x80>,
@@ -843,37 +311,6 @@ 
			ti,timer-pwm;

		};



		timer9: timer@4803e000 {

			compatible = "ti,omap5430-timer";

			reg = <0x4803e000 0x80>;

			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "timer9";

			ti,timer-pwm;

		};



		timer10: timer@48086000 {

			compatible = "ti,omap5430-timer";

			reg = <0x48086000 0x80>;

			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "timer10";

			ti,timer-pwm;

		};



		timer11: timer@48088000 {

			compatible = "ti,omap5430-timer";

			reg = <0x48088000 0x80>;

			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "timer11";

			ti,timer-pwm;

		};



		wdt2: wdt@4ae14000 {

			compatible = "ti,omap5-wdt", "ti,omap3-wdt";

			reg = <0x4ae14000 0x80>;

			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "wd_timer2";

		};



		dmm@4e000000 {

			compatible = "ti,omap5-dmm";

			reg = <0x4e000000 0x800>;
@@ -905,99 +342,6 @@ 
			hw-caps-temp-alert;

		};



		usb3: omap_dwc3@4a020000 {

			compatible = "ti,dwc3";

			ti,hwmods = "usb_otg_ss";

			reg = <0x4a020000 0x10000>;

			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <1>;

			utmi-mode = <2>;

			ranges;

			dwc3: dwc3@4a030000 {

				compatible = "snps,dwc3";

				reg = <0x4a030000 0x10000>;

				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-names = "peripheral",

						  "host",

						  "otg";

				phys = <&usb2_phy>, <&usb3_phy>;

				phy-names = "usb2-phy", "usb3-phy";

				dr_mode = "peripheral";

			};

		};



		ocp2scp@4a080000 {

			compatible = "ti,omap-ocp2scp";

			#address-cells = <1>;

			#size-cells = <1>;

			reg = <0x4a080000 0x20>;

			ranges;

			ti,hwmods = "ocp2scp1";

			usb2_phy: usb2phy@4a084000 {

				compatible = "ti,omap-usb2";

				reg = <0x4a084000 0x7c>;

				syscon-phy-power = <&scm_conf 0x300>;

				clocks = <&usb_phy_cm_clk32k>,

					 <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;

				clock-names = "wkupclk", "refclk";

				#phy-cells = <0>;

			};



			usb3_phy: usb3phy@4a084400 {

				compatible = "ti,omap-usb3";

				reg = <0x4a084400 0x80>,

				      <0x4a084800 0x64>,

				      <0x4a084c00 0x40>;

				reg-names = "phy_rx", "phy_tx", "pll_ctrl";

				syscon-phy-power = <&scm_conf 0x370>;

				clocks = <&usb_phy_cm_clk32k>,

					 <&sys_clkin>,

					 <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;

				clock-names =	"wkupclk",

						"sysclk",

						"refclk";

				#phy-cells = <0>;

			};

		};



		usbhstll: usbhstll@4a062000 {

			compatible = "ti,usbhs-tll";

			reg = <0x4a062000 0x1000>;

			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "usb_tll_hs";

		};



		usbhshost: usbhshost@4a064000 {

			compatible = "ti,usbhs-host";

			reg = <0x4a064000 0x800>;

			ti,hwmods = "usb_host_hs";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;

			clocks = <&l3init_60m_fclk>,

				 <&xclk60mhsp1_ck>,

				 <&xclk60mhsp2_ck>;

			clock-names = "refclk_60m_int",

				      "refclk_60m_ext_p1",

				      "refclk_60m_ext_p2";



			usbhsohci: ohci@4a064800 {

				compatible = "ti,ohci-omap3";

				reg = <0x4a064800 0x400>;

				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;

				remote-wakeup-connected;

			};



			usbhsehci: ehci@4a064c00 {

				compatible = "ti,ehci-omap";

				reg = <0x4a064c00 0x400>;

				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;

			};

		};



		bandgap: bandgap@4a0021e0 {

			reg = <0x4a0021e0 0xc

			       0x4a00232c 0xc
@@ -1010,27 +354,6 @@ 
		};



		/* OCP2SCP3 */

		ocp2scp@4a090000 {

			compatible = "ti,omap-ocp2scp";

			#address-cells = <1>;

			#size-cells = <1>;

			reg = <0x4a090000 0x20>;

			ranges;

			ti,hwmods = "ocp2scp3";

			sata_phy: phy@4a096000 {

				compatible = "ti,phy-pipe3-sata";

				reg = <0x4A096000 0x80>, /* phy_rx */

				      <0x4A096400 0x64>, /* phy_tx */

				      <0x4A096800 0x40>; /* pll_ctrl */

				reg-names = "phy_rx", "phy_tx", "pll_ctrl";

				syscon-phy-power = <&scm_conf 0x374>;

				clocks = <&sys_clkin>,

					 <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;

				clock-names = "sysclk", "refclk";

				#phy-cells = <0>;

			};

		};



		sata: sata@4a141100 {

			compatible = "snps,dwc-ahci";

			reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
@@ -1184,6 +507,7 @@ 
	coefficients = <65 (-1791)>;

};



#include "omap5-l4.dtsi"

#include "omap54xx-clocks.dtsi"



&gpu_thermal {

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