Commit 4c2d4222 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/core: have fifo store a unique context identifier at attach time 



This value will match something that's easily available from the engine IRQ
handlers, and used to lookup the relevant context.

Since the changes in how this is done on each generation match when the
major PFIFO changes happened, fifo is responsible for calculating the
correct value to avoid duplicating the same code among many engine modules.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 0c5b8cec

drivers/gpu/drm/nouveau/core/core/engctx.c

+1 −0
Original line number Diff line number Diff line
@@ -105,6 +105,7 @@ nouveau_engctx_create_(struct nouveau_object *parent, 
	if (client->vm)

		atomic_inc(&client->vm->engref[nv_engidx(engobj)]);

	list_add(&nv_engctx(engctx)->head, &engine->contexts);

	nv_engctx(engctx)->addr = ~0ULL;

	spin_unlock_irqrestore(&engine->lock, save);

	return 0;

}

drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c

+9 −0
Original line number Diff line number Diff line
@@ -102,6 +102,14 @@ nv04_fifo_object_detach(struct nouveau_object *parent, int cookie) 
	mutex_unlock(&nv_subdev(priv)->mutex);

}



int

nv04_fifo_context_attach(struct nouveau_object *parent,

			 struct nouveau_object *object)

{

	nv_engctx(object)->addr = nouveau_fifo_chan(parent)->chid;

	return 0;

}



static int

nv04_fifo_chan_ctor(struct nouveau_object *parent,

		    struct nouveau_object *engine,
@@ -127,6 +135,7 @@ nv04_fifo_chan_ctor(struct nouveau_object *parent, 


	nv_parent(chan)->object_attach = nv04_fifo_object_attach;

	nv_parent(chan)->object_detach = nv04_fifo_object_detach;

	nv_parent(chan)->context_attach = nv04_fifo_context_attach;

	chan->ramfc = chan->base.chid * 32;



	nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset);

drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c

+1 −0
Original line number Diff line number Diff line
@@ -78,6 +78,7 @@ nv10_fifo_chan_ctor(struct nouveau_object *parent, 


	nv_parent(chan)->object_attach = nv04_fifo_object_attach;

	nv_parent(chan)->object_detach = nv04_fifo_object_detach;

	nv_parent(chan)->context_attach = nv04_fifo_context_attach;

	chan->ramfc = chan->base.chid * 32;



	nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset);

drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c

+1 −0
Original line number Diff line number Diff line
@@ -85,6 +85,7 @@ nv17_fifo_chan_ctor(struct nouveau_object *parent, 


	nv_parent(chan)->object_attach = nv04_fifo_object_attach;

	nv_parent(chan)->object_detach = nv04_fifo_object_detach;

	nv_parent(chan)->context_attach = nv04_fifo_context_attach;

	chan->ramfc = chan->base.chid * 64;



	nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset);

drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c

+3 −2
Original line number Diff line number Diff line
@@ -128,11 +128,12 @@ nv40_fifo_context_attach(struct nouveau_object *parent, 
	}



	spin_lock_irqsave(&priv->base.lock, flags);

	nv_engctx(engctx)->addr = nv_gpuobj(engctx)->addr >> 4;

	nv_mask(priv, 0x002500, 0x00000001, 0x00000000);



	if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid)

		nv_wr32(priv, reg, nv_gpuobj(engctx)->addr >> 4);

	nv_wo32(priv->ramfc, chan->ramfc + ctx, nv_gpuobj(engctx)->addr >> 4);

		nv_wr32(priv, reg, nv_engctx(engctx)->addr);

	nv_wo32(priv->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr);



	nv_mask(priv, 0x002500, 0x00000001, 0x00000001);

	spin_unlock_irqrestore(&priv->base.lock, flags);

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