Commit 4c020a96 authored Mar 03, 2010 by David Dillow Committed by David S. Miller Mar 04, 2010

r8169: use correct barrier between cacheable and non-cacheable memory



r8169 needs certain writes to be visible to other CPUs or the NIC before
touching the hardware, but was using smp_wmb() which is only required to
order cacheable memory access. Switch to wmb() which is required to
order both cacheable and non-cacheable memory.

Noticed by Catalin Marinas and Paul Mackerras.

Signed-off-by: David Dillow <dave@thedillows.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent d0021b25

drivers/net/r8169.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -4270,7 +4270,7 @@ static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,

		tp->cur_tx += frags + 1;

		smp_wmb();
		wmb();

		RTL_W8(TxPoll, NPQ); /* set polling bit */

		@@ -4621,7 +4621,7 @@ static int rtl8169_poll(struct napi_struct *napi, int budget)
		* until it does.
		*/
		tp->intr_mask = 0xffff;
		smp_wmb();
		wmb();
		RTL_W16(IntrMask, tp->intr_event);
		}

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